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| msp 3400c multistandard sound processor edition dec. 8, 1997 6251-377-3pd prelimina r y d a t a sheet mic r onas micronas
preliminary data sheet msp 3400c 2 micronas contents page section title 5 1. introduction 6 2. features of the msp 3400c 6 2.1. features of the demodulator and decoder sections 6 2.2. features of the dsp-section 6 2.3. features of the analog section 7 3. application fields of the msp 3400c 7 3.1. german 2-carrier system (dual fm system) 9 4. architecture of the msp 3400c 9 4.1. demodulator block 9 4.1.1. analog sound if ? input section 9 4.1.2. quadrature mixers 10 4.1.3. lowpass filtering block for mixed sound if signals 10 4.1.4. phase and am discrimination 10 4.1.5. differentiators 10 4.1.6. lowpass filter block for demodulated signals 10 4.1.7. high deviation fm mode 10 4.1.8. mspc-mute function in the dual carrier fm mode 11 4.2. analog section and scart switching facilities 11 4.3. msp 3400c audio baseband processing 11 4.3.1. dual carrier fm stereo/bilingual detection 13 4.4. audio pll and crystal specifications 13 4.5. adr bus 14 4.6. s-bus interface 15 4.7. i 2 s bus interface 16 5. i 2 c bus interface: device and subaddresses 17 5.1. protocol description 18 5.2. proposal for msp 3400c i 2 c telegrams 18 5.2.1. symbols 18 5.2.2. write telegrams 18 5.2.3. read telegrams 18 5.2.4. examples 19 5.3. start up sequence 20 6. programming the demodulator part 20 6.1. registers: table and addresses 21 6.2. registers: functions and values 21 6.2.1. setting of parameter ad_cv 23 6.2.2. control register ?mode_reg? 24 6.2.3. fir-filter switches 24 6.2.4. fir-parameter 26 6.2.5. dco-increments msp 3400c preliminary data sheet 3 micronas contents, continued page section title 27 6.3. sequences to transmit parameters and to start processing 27 6.4. software proposals for multistandard tv-sets 27 6.4.1. multistandard system b/g german dual fm 28 6.4.2. satellite mode 28 6.4.3. automatic search function for fm-carrier detection 28 6.4.4. automatic standard detection 29 7. programming the audio processing part 29 7.1. summary of the dsp control registers 31 7.1.1. volume loudspeaker channel and headphone channel 32 7.1.2. balance loudspeaker and headphone channel 33 7.1.3. bass loudspeaker and headphone channel 33 7.1.4. treble l oudspeaker and headphone channel 34 7.1.5. loudness loudspeaker and headphone channel 34 7.1.6. spatial effects loudspeaker channel 35 7.1.7. volume scart 35 7.1.8. channel source modes 36 7.1.9. channel matrix modes 36 7.1.10. scart prescale 36 7.1.11. fm prescale 37 7.1.12. fm matrix modes 37 7.1.13. fm fixed deemphasis 37 7.1.14. fm adaptive deemphasis 37 7.1.15. i 2 s1 and i 2 s2 prescale 37 7.1.16. acb register, definition of the scart-switches and dig_ctr_out pins 38 7.1.17. beeper 38 7.1.18. identification mode 38 7.1.19. fm dc notch 38 7.1.20. mode tone control 39 7.1.21. equalizer loudspeaker channel 39 7.1.22. automatic volume correction (avc) 40 7.1.23. subwoofer on headphone output 40 7.2. exclusions 41 7.3. summary of readable registers 41 7.3.1. stereo detection register 41 7.3.2. quasi peak detector 42 7.3.3. dc level register 42 7.3.4. msp hardware version code 42 7.3.5. msp major revision code 42 7.3.6. msp product code 42 7.3.7. msp rom version code preliminary data sheet msp 3400c 4 micronas contents, continued page section title 43 8. specifications 43 8.1. outline dimensions 44 8.2. pin connections and descriptions 48 8.3. pin configuration 51 8.4. pin circuits 53 8.5. electrical characteristics 53 8.5.1. absolute maximum ratings 54 8.5.2. recommended operating conditions 58 8.5.3. characteristics 64 9. application of the msp 3400c 65 10. dma application 67 11. msp application with external clock 67 12. adr application 68 13. i 2 s bus in master/slave configuration with standby mode 69 14. appendix a: technical code history 69 15. appendix b: documentation history msp 3400c preliminary data sheet 5 micronas multistandard sound processor release notes: the hardware description in this document is valid for the msp 3400c ? c8 and newer codes. revision bars indicate significant changes to the previous version. 1. introduction the msp 3400c is designed as single-chip multistan- dard sound processor for applications in analog and digital tv sets, satellite receivers and video recorders. the msp-family, which is based on the msp 2400, dem- onstrates the progressive development towards highly integrated multi-functional ics. the msp 3400c, again, improves function integration: the full tv sound processing, starting with analog sound if signal-in, down to processed analog af-out, is performed in a single chip. the ic is produced in 0.8 m cmos technology, combined with high performance digital signal processing. the msp 3400c 0.8 cmos version is fully pin and software compatible to the 1.0 msp 3400 and msp 3410. the main difference between the msp 3400c and the msp 3410, consists of the msp 3410 being able to decode nicam signals. the msp 3400c is available in plcc68, psdip64, psdip52, and pqfp80 package. note: to achieve compatibility with the functions of msp 3400 and msp 3410 (except nicam), the load se- quences must be programmed as described in the data sheet of msp 3410. msp 3400c integrated functions: ? fm-demodulation of all terrestrial standards (incl. identification decoding) ? fm-demodulation of all satellite standards ? various deemphasis types (incl. panda1) ? volume, balance, bass, treble, loudness for loudspeaker and headphone output ? automatic volume correction (a.v.c.) ? 5 band graphic equalizer ? subwoofer output alternatively with headphone output ? spatial effect (pseudostereo/basewidth enlargement) ? adr together with drp 3510 a ? dolby prologic together with dpl 3418/19/20 a ? 3 pairs of d/a converters ? 1 pair of a/d converters ? scart switches sound if 1 sound if 2 mono in scart1 in 2 scart2 in 2 scart3 in 2 2 scart1 out 2 scart2 out 2 loudspeaker out 2 headphone out msp 3400c i 2 si 2 c 2 5 fig. 1?1: main i/o signals msp 3400c adr/sbus 3 preliminary data sheet msp 3400c 6 micronas 2. features of the msp 3400c 2.1. features of the demodulator and decoder sections the msp 3400c is designed to perform demodulation of fm-mono tv sound and two carrier fm systems ac- cording to the german or korean terrestrial specs. with certain constraints, it is also possible to do am-demodu- lation according to the secam system. alternatively, the satellite specs can be processed with the msp 3400c. for fm carrier detection in satellite operation, the am- demodulation offers a powerful feature to calculate the carrier field strength, which can be used for automatic search algorithms. so, the ic facilitates a first step to- wards multistandard capability with its very flexible application and may be used in tv-sets, satellite tuners, and video recorders. the msp 3400c facilitates profitable multistandard ca- pability, offering the following advantages: ? two selectable analog inputs (tv and sat-if sources) ? automatic gain control (agc) for analog input: input range: 0.14 ? 3 vpp ? integrated a/d converter for sound-if inputs ? all demodulation and filtering is performed on chip and is individually programmable ? no external filter hardware is required ? only one crystal clock (18.432 mhz) is necessary ? fm carrier level calculation for automatic search algo- rithms and carrier mute function ? high deviation fm-mono mode (max. deviation: approx. 360 khz) 2.2. features of the dsp-section ? flexible selection of audio sources to be processed ? digital input and output interfaces via i 2 s-bus for exter- nal dsp-processors, surround sound, adr etc. ? digital interface to process adr (astra digital radio) together with drp 3510 a ? performance of all deemphasis systems including adaptive wegener panda 1 without external compo- nents or controlling ? digitally performed fm-identification decoding and de- matrixing ? digital baseband processing: volume, bass, treble, 5-band equalizer, loudness, pseudostereo, and base- width enlargement ? simple controlling of volume, bass, treble, equalizer etc. ? increased audio bandwidth for fm-audio-signals (20 hz ? 15 khz, 1 db) 2.3. features of the analog section ? three selectable analog pairs of audio baseband in- puts (= three scart inputs) input level: 2 v rms, input impedance: 25 k ? ? one selectable analog mono input (i.e. am sound), input level: 2 v rms, input impedance: 10 k ? ? two high quality a/d converters, s/n-ratio: 85 db ? 20 hz to 20 khz bandwidth for scart-to-scart- copy facilities ? main (loudspeaker) and aux (headphones): two pairs of 4-fold oversampled d/a-converters output level per channel: max. 1.4 v rms output resistance: max. 5 k ? s/n-ratio: 85 db at maximum volume max. noise voltage in mute mode: 10 v (bw: 20 hz ...16 khz) ? one pair of four-fold oversampled d/a-converters sup- plying two selectable pairs of scart-outputs. output level per channel: max. 2 v rms, output resistance: max. 0.5 k ? , s/n-ratio: 85 db (20 hz...16 khz) msp 3400c preliminary data sheet 7 micronas 3. application fields of the msp 3400c the msp 3400c processes tv sound according to the german and korean two carrier system and the com- monly used satellite systems. in the following sections, a brief overview on the german fm-stereo system shows what is required of a multistandard audio ic. 3.1. german 2-carrier system (dual fm system) since september 1981, stereo and dual sound pro- grams have been transmitted in germany using the 2-carrier system. sound transmission consists of the al- ready existing first sound carrier and a second sound carrier additionally containing an identification signal. more details of this standard are given in table 3 ? 1. table 3 ? 1: european tv standards tv-system position of sound carrier /mhz sound modulation color system country b/g 5.5/5.7421875 fm-stereo pal germany b/g 5.5/5.85 fm-mono/nicam pal scandinavia,spain l 6.5/5.85 am-mono/nicam secam-l france i 6.0/6.552 fm-mono/nicam pal uk d/k 6.5 /6.2578125 d/k1 6.5/6.7421875 d/k2 6.5/5.85 d/k-nicam fm-stereo fm-mono/nicam secam-east ussr hungary m m-korea 4.5 4.5/4.724212 fm-mono fm-stereo ntsc usa korea satellite satellite 6.5 7.02/7.2 fm-mono fm-stereo pal pal europe (astra) europe (astra) tuner sound if mixer vision demo- dulator composite video scart1 scart2 scart3 scart1 scart2 optional feature processor amu and dma or drp saw filter sound if filter msp 3400c 33 34 39 mhz 59mhz loudspeaker headphone am sound 2 2 2 2 2 i 2 s sbus / adr scart inputs scart outputs fig. 3 ? 1: typical msp 3400c application according to the mixing characteristics of the sound-if-mixer, the sound-if filter may be omitted. i 2 s preliminary data sheet msp 3400c 8 micronas table 3 ? 2: key parameters for b/g, d/k, and m 2-carrier sound system sound carriers carrier fm1 carrier fm2 b/g d/k m b/g d/k m vision/sound power difference 13 db 20 db sound bandwidth 40 hz to 15 khz pre-emphasis 50 s 75 s 50 s 75 s frequency deviation 50 khz 25 khz 50 khz 25 khz sound signal components mono transmission mono mono stereo transmission (l+r)/2 (l+r)/2 r (l ? r)/2 dual sound transmission language a language b identification of transmission mode on carrier fm2 pilot carrier frequency in khz 54.6875 55.0699 type of modulation am modulation depth 50% modulation frequency mono: unmodulated stereo: 117.5 hz dual: 274.1 hz 149.9 hz 276.0 hz note: nicam decoding can be achieved by using the msp 3410 instead of the msp 3400c. since the msp 3400c and the msp 3410 are fully pin and soft- ware downwards compatible (concerning all features of msp 3410), it is possible to decide in the assembly line, whether the application should be able to decode nicam or not. msp 3400c preliminary data sheet 9 micronas 4. architecture of the msp 3400c fig. 4 ? 1 shows a simplified block diagram of the ic. its architecture is split into three functional blocks: 1. demodulator section 2. digital signal processing (dsp) section performing audio baseband processing 3. analog section containing two a/d-converters, 6 d/a-converters, and scart switching facilities 4.1. demodulator block 4.1.1. analog sound if ? input section the input pins ana_in1+, ana_in2+, and ana_in ? offer the possibility to connect two different sound if sources to the msp 3400c. by means of bit [8] of ad_cv (see table 6 ? 3), either terrestrial or satellite sound if signals can be selected. the analog-to-digital conversion of the preselected sound if signal is done by a flash-converter, whose output can be used to control an automatic gain circuit (agc), providing optimum level for a wide range of input levels. it is possible to switch between automatic gain control and a fixed (setable) in- put gain. in the optimum case, the input range of the a/d converter is completely covered by the sound if source. some combinations of saw filters and sound if mixer ics, however, show large picture components on their outputs. in this case, filtering is recommended. it was found that the high pass filters formed by the coupling capacitors at pins ana_in1+ and ana_in2+ as shown in the application diagram are sufficient in most cases. 4.1.2. quadrature mixers the digital input coming from the integrated a/d conver- ter may contain audio information at a frequency range of theoretically 0 to 9 mhz corresponding to the selected standards. by means of two programmable quadrature mixers two different audio sources, for example fm1 and fm2, may be shifted into baseband position. in the following, the two main channels are provided to pro- cess either: ? fm mono (channel 2) or ? fm2 (channel 1) and fm1 (channel 2). two independent digital oscillators are provided to gen- erate two pairs of sin/cos-functions. two programmable increments, to be divided up into low- and high part, de- termine frequency of the oscillator, which corresponds to the frequency of the desired audio carrier. in section 6.1., format and values of the increments are listed. demodulator dfp sound if loudspeaker dacm_l daca_l sc1_out_l headphone mono scart1 scart2 d/a d/a d/a d/a d/a d/a scart3 scart 1 scart 2 fm1 / am fm2 scart_l scart_r scart_l scart_r i2sl/r headphone l headphone r loud- speaker r loud- speaker l ident a/d a/d dacm_r daca_r sc1_out_r sc2_out_l sc2_out_r ana_in1+ ana_in2+ mono_in sc1_in_l sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r s_cl / adr_cl s_da_in / adr_da i2s_ws sbus/adr interface fig. 4 ? 1: architecture of the msp 3400c scart switching facilities i2s1/2l/r i2s_cl i2s_da_in_1/2 i2s_da_out i 2 s interface s_id / adr_ws s1..4 xtal_in aud_cl_out audio pll xtal_out preliminary data sheet msp 3400c 10 micronas fig. 4 ? 2: demodulator architecture agc ad mixer lowpass phase and am dis- crimination differen- tiator lowpass mute carrier detect mixer lowpass phase and am dis- crimination differen- tiator lowpass mute carrier detect fm2 fm1/am ana_in1+ ana_in2+ oscillator dco1 fir_reg_1 ad_cv[7:1] ad_cv[8] dco2 fir_reg_2 mode_reg[8] ad_cv[9,10,11] oscillator phase phase amplitude amplitude pins internal signal lines control registers mspc sound if channel 1 (msp-ch1: fm2) mspc sound if channel 2 (msp-ch2: fm1, am) frame fm2 dco2 mixer ident vreftop ana_in? mode_reg[8] adr_da 4.1.3. lowpass filtering block for mixed sound if signals fm bandwidth limitation is performed by a linear phase finite impulse response (fir-filter). just like the oscil- lators ? increments, the filter coefficients are program- mable and are written into the ic by the ccu via the con- trol bus. two not necessarily different sets of coefficients are required, one for channel 1 (fm2) and one for chan- nel 2 (fm1=fm-mono). in section 6.2.4., several coeffi- cient sets are proposed. 4.1.4. phase and am discrimination the filtered sound if signals are demodulated by means of the phase and amplitude discriminator block. on the output, the phase and amplitude is available for further processing. am signals are derived from the amplitude information, whereas the phase information serves for fm demodulation. 4.1.5. differentiators fm demodulation is completed by differentiating the phase information output. 4.1.6. lowpass filter block for demodulated signals the demodulated fm and am signals are further low- pass filtered and decimated to a final sampling frequen- cy of 32 khz. the usable bandwidth of the final base- band signals is about 15 khz. 4.1.7. high deviation fm mode by means of mode_reg [9], the maximum fm-devi- ation can be extended to approximately 360 khz. since this mode can be applied only for the mspc sound if channel 2, the corresponding matrices in the base- band processing must be set to sound a. apart from this, the coefficient sets 380 khz fir_reg2 or 500 khz fir_reg2 must be chosen for the fir_reg_2. for a given deviation, in relation to the normal fm-mode, the audio level of the high-deviation mode is reduced by 6 db. 4.1.8. mspc-mute function in the dual carrier fm mode to prevent noise effects or fm identification problems in the absence of one of the two fm carriers, the msp 3400 c offers a carrier detection feature, which must be activated by means of ad_cv[9]. the mute lev- el may be programmed by means of ad_cv[10,11]. (see section 6.2.1.) if no fm carrier is available at the mspc channel 1, the corresponding channel fm2 is muted. if no fm carrier is available at the mspc channel 2, the corresponding channel fm1 is muted. in case of the absence of both fm carriers, pure noise will be am- plified by the input agc. therefore, a proper mute func- tion depends on the noise quality of the tv set ? s if part and cannot be guaranteed. the mute function is not rec- ommended for the satellite mode. msp 3400c preliminary data sheet 11 micronas 4.2. analog section and scart switching facilities the analog input and output sections offer a wide range of switching facilities, which are shown in fig. 4 ? 3. to design a tv-set with 3 pairs of scart-inputs and two pairs of scart-outputs, no external switching hardware is required. the switches are controlled by the acb bits defined in the audio processing interface (see section 7. program- ming the audio processing part). if the msp 3400c is switched off by first pulling stand- byq low, and then disconnecting the 5 v, but keeping the 8 v power supply ( ? standby ? -mode ), the switches s1, s2, and s3 maintain their position and function. this facilitates the copying from selected scart-inputs to scart-outputs in the tv-sets standby mode. scart_in sc1_in_l/r sc2_in_l/r sc3_in_l/r mono from audio baseband processing (dfp) scartl/r scart_out sc1_out_l/r sc2_out_l/r 2 2 2 2 2 2 2 s1 s2 s3 2 2 2 2 2 2 2 2 acb [1:0] acb [3:2] acb [5:4] 00 01 10 11 11 01 10 00 00 01 10 scartl/r to audio baseband processing (dfp) fig. 4 ? 3: scart-switching facilities bold lines determine the default configuration d a a d in case of power-on start or starting from standby, the ic switches automatically to the default configuration, shown in fig. 4 ? 3. this takes place after the first i 2 c transmission into the dfp part. by transmitting the acb register first, the default setting mode can be changed. 4.3. msp 3400c audio baseband processing by means of the dfp processor, all audio baseband functions are performed by digital signal processing (dsp). the dsp functions are grouped into three pro- cessing parts: input preprocessing, channel selection, and channel postprocessing. the input preprocessing is intended to prepare the vari- ous signals of all input sources in order to form a stan- dardized signal at the input to the channel selector. the signals can be adjusted in volume, are processed with the appropriate deemphasis, and are dematrixed if nec- essary. having prepared the signals that way, the channel selec- tor makes it possible to distribute all possible source sig- nals to the desired output channels. the ability to route in an external coprocessor for special effects like surround and sound field processing is of special importance. routing can be done with each input source and output channel via the i 2 s inputs and out- puts. all input and output signals can be processed simulta- neously. note that the nicam input signals are only available in the msp 3410 version. while processing the adaptive deemphasis, no dual carrier stereo (german or korean) is possible. identification values are not valid ei- ther. 4.3.1. dual carrier fm stereo/bilingual detection in the german and korean tv standard, audio informa- tion can be transmitted in three modes: mono, stereo, or bilingual. to obtain information about the current audio operation mode, the msp 3400c detects the so-called identification signal. information is supplied via the ste- reo detection register to an external ccu. ident am demodu- lation stereo detection register stereo detection filter bilingual detection filter level detect level detect ? fig. 4 ? 4: stereo/bilingual detection msp 3400c preliminary data sheet 12 micronas analog inputs demodulated if inputs i 2 s bus inputs fm adaptive deemphasis deemphasis 50/75 s j17 fm-matrix scart channel matrix volume scart_l scart_r channel select scart outputs i 2 s outputs quasi-peak detector scartl scartr i 2 s1l i 2 s1r i 2 s2l i 2 s2r fm1 fm2 quasi peak readout r dc level readout fm2 dc level readout fm1 quasi peak readout l fig. 4 ? 5: audio baseband processing (dsp-firmware) scart i 2 s channel matrix i 2 sr i 2 sl i 2 s2 i 2 s1 quasi-peak- channel matrix sbus inputs sbus1 sbus2 sbus3 sbus4 volume volume loudspeaker l loudspeaker r headphone l headphone r loudspeake r outputs headphone outputs beeper loudspeaker channel matrix loudness spatial effects bass/ treble or equalizer subwoofer level adjust lowpass balance headphone channel matrix loudness bass/ treble balance avc comple- mentary highpass prescale prescale prescale prescale msp 3400c preliminary data sheet 13 micronas table 4 ? 1: several examples for recommended channel assignments for demodulator and audio processing part mode mspc sound if- channel 1 / fm2 mspc sound if- channel 2 / fm1 fm- matrix channel select channel matrix b/g-stereo fm2 (5.74 mhz): r fm1 (5.5 mhz): (l+r)/2 b/g stereo speakers: fm stereo b/g-bilingual fm2 (5.74 mhz): sound b fm1 (5.5 mhz): sound a no matrix speakers: fm h.phone : fm speakers: sound a h.phone : sound b sat-mono not used fm (6.5 mhz): mono no matrix speakers: fm sound a sat-stereo 7.20 mhz: r 7.02 mhz: l no matrix speakers: fm stereo sat-bilingual 7.38 mhz: sound c 7.02 mhz: sound a no matrix speakers: fm h.phone : fm speakers: sound a h.phone :sound b=c sat high dev. mode (e.g. eutelsat) don ? t care 6.552 mhz no matrix speakers: fm h.phone : fm speakers: sound a h.phone : sound a 4.4. audio pll and crystal specifications the msp 3400c runs at 18.432 mhz. a detailed specifi- cation of the required crystal for different packages and master/slave applications can be found in table 8.5.2. the clock supply of the entire system depends on the msp 3400c operation mode: 1. fm-stereo/i 2 s master operation: the system clock runs free on the crystal ? s 18.432 mhz. 2. i 2 s slave operation: in this case, the system clock is synchronizing on the i 2 s_ws signal, which is fed into the msp 3400c (mode_reg[3] = 1). 3. d2-mac operation: in this case, the system clock is locked to a synchroniz- ing signal (dma_sync) supplied by the d2-mac chip (mode_reg[0] = 1). the dma and the amu chips can be driven by the msp 3400c audio clock (aud_cl_out). remark on using the crystal: external capacitors at each crystal pin to ground are re- quired. they are necessary for tuning the open-loop fre- quency of the internal pll and for stabilizing the fre- quency in closed-loop operation. the higher the capacitors, the lower the clock frequency results. the nominal free running frequency should match the center of the tolerance range between 18.433 and 18.431 mhz as closely as possible. due to different layouts of cus- tomer pcbs, the matching capacitor size should be de- fined in the application (see also table 8.5.2.). 4.5. adr bus to be able to process adr, the mspc has a special de- signed interface to work together with drp 3510a. to be prepared for an upgrade to adr with an additional drp board, the following lines of msp 3400c should be pro- vided on a feature connector: ? aud_cl_out ? i 2 s_da_in1 or i 2 s_da_in2 ? i 2 s_da_out ? i 2 s_ws ? i 2 s_clk ? s_cl = adr_cl ? s_id = adr_ws ? s_da_in = adr_da preliminary data sheet msp 3400c 14 micronas 4.6. s-bus interface digital audio information provided by the dma 2381 via the amu is serially transmitted to the msp 3400c via the s-bus. the msp 3400c is always in s-bus master mode. the s-bus interface consists of three pins: 1. s_da_in: four channels (4*16 bits) per sampling cycle (32 khz) are transmitted. 2. s_cl: gives the timing for the transmission of s-data (4.608 mhz). 3. s_id: after 64 s-clock cycles, the s_id determines the end of one sampling period. a detailed timing diagram is shown in fig. 4 ? 6. h l h l h l s-ident s-clock s-data 16 bit sound 1 a 16 bit sound 2 16 bit sound 3 16 bit sound 4 64 clock cycles b (data: msb first) section a h l s-data h l s-clock h l s-ident lsb of sound 1 t s1 t s2 t s4 t s5 4.608 mhz section b msb of sound 4 t s3 t s6 h l s-data h l s-clock h l s-ident 4.608 mhz fig. 4 ? 6: s-bus timing diagram msp 3400c preliminary data sheet 15 micronas 4.7. i 2 s bus interface by means of this standardized interface, additional fea- ture processors can be connected to the msp 3400c. two possible formats are supported: the standard mode (mode_reg[4]=0) selects the sony format, where the i2s_ws signal changes at the word bound- aries. the so-called philips format, which is character- ized by a change of the i2s_ws signal, one i2s_cl peri- od before the word boundaries, is selected by setting mode_reg[4]=1. the msp 3400c normally serves as the master on the i 2 s interface. here, the clock and word strobe lines are driven by the msp 3400c. by setting mode_reg[3]=1, the msp 3400c is switched to a slave mode. now, these lines are input to the msp 3400 c, and the master clock is synchronized to 576 times the i2s_ws rate (32 khz). no d2mac operation is possible in this mode. the i 2 s bus interface consists of five pins: 1. i2s_da_in1: for input, two channels (2*16 bits) per sampling cycle (32 khz) are transmitted. 2. i2s_da_in2: for input, two channels (2*16 bits) per sampling cycle (32 khz) are transmitted. 3. i2s_da_out: for output, two channels (2*16 bits) per sampling cycle (32 khz) are transmitted. 4. i2s_cl: gives the timing for the transmission of i 2 s serial data (1.024 mhz). 5. i2s_ws: the i2s_ws word strobe line defines the left and right sample. a detailed timing diagram is shown in fig. 4 ? 7. philips mode i 2 s_ws i 2 s_cl i 2 s_dain i 2 s_daout sony mode sony mode philips mode detail c detail a detail b 16 bit left channel 16 bit left channel 16 bit right channel 16 bit right channel i 2 s_cl i 2 s_ws as input i 2 s_ws as output philips/sony mode programmable by mode_reg[4] f i2scl t i2sws1 t i2sws2 t i2s5 t i2s6 t i2s2 t i2s3 t i2s4 t i2s1 detail c detail a,b f i2sws i 2 s_cl i 2 s_da_in i 2 s_da_out r lsb l msb r lsb l msb l lsb r msb l lsb r msb r lsb l lsb r lsb l lsb fig. 4 ? 7: i 2 s bus timing diagram ( data: msb first) preliminary data sheet msp 3400c 16 micronas 5. i 2 c bus interface: device and subaddresses as a slave receiver, the msp 3400c can be controlled via i 2 c bus. access to internal memory locations is achieved by subaddressing. the demodulator part and the audio processor part (dfp) have two separate sub- addressing register banks. in order to allow for more msp 3400c ics to be con- nected to the control bus, an adr_sel pin has been im- plemented. with adr_sel pulled to high, the msp 3400c responds to changed device addresses, thus two identical devices can be selected. other devices of the same family will have different subaddresses (e.g. 34x0) by means of the reset bit in the control register, all devices with the same device address are reset. the ic is selected by asserting a special device address in the address part of an i 2 c transmission. a device ad- dress pair is defined as a write address (80 hex or 84 hex) and a read address (81 hex or 85 hex). writing is done by sending the device write address first, followed by the subaddress byte, two address bytes, and two data bytes. for reading, the read address has to be transmitted first by sending the device write address (80 hex or 84 hex), followed by the subaddress byte, and two address bytes. without sending a stop condition, read- ing of the addressed data is done by sending the device read address (81 hex or 85 hex) and reading two bytes of data. refer to fig. 5 ? 1 i 2 c bus protocol and section 5.2. proposal for msp 3400c i 2 c telegrams. due to the internal architecture of the msp 3400c, the ic cannot react immediately to an i 2 c request. the typi- cal response time is about 0.3 ms. if the addressed pro- cessor is not ready for further transmissions on the i 2 c bus, the clock line i2c_cl is pulled low. this puts the current transmission into a wait state. after a certain pe- riod of time, the msp 3400c releases the clock, and the interrupted transmission is carried on. the i 2 c bus lines can be set tristate by switching the ic into ? standby ? -mode. i 2 c-bus error conditions: in case of any internal error, the msp ? s wait-period is ex- tended to 1.77 ms. afterwards, the msp does not ac- knowledge (nak) the device address. the data line will be left high by the msp, and the clock line will be re- leased. the master can then generate a stop condition to abort the transfer. by means of nak, the master is able to recognize the er- ror state and to reset the ic via i 2 c-bus. while transmit- ting the reset protocol (section. 5.2.4.) to ? control ? , the master must ignore the not acknowledge bits (nak) of the msp. a detailed timing diagram is shown in fig. 5 ? 1 and fig. 5 ? 2. table 5 ? 1: i 2 c bus device addresses adr_sel low high left open mode write read write read write read msp device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex table 5 ? 2: i 2 c bus device and subaddresses name binary value hex value function control 0000 0000 00 software reset test1 0000 0001 01 only for internal use test2 0000 0010 02 only for internal use wr_dem 0001 0000 10 write address demodulator rd_dem 0001 0001 11 read address demodulator wr_dfp 0001 0010 12 write address dfp rd_dfp 0001 0011 13 read address dfp agc 0001 1110 1e read agc rms pll_cap 0001 1111 1f read / write pll_cap msp 3400c preliminary data sheet 17 micronas table 5 ? 3: control register name 15 14..0 control reset 0 5.1. protocol description write to dfp or demodulator part (long protocol) s daw wait ack sub-addr ack addr-byte high ack addr-byte low ack data-byte high ack data-byte low ack p read from dfp part (long protocol) s daw wait ack sub-addr ack addr-byte high ack addr-byte low ack s dar wait ack data-byte high ??? ? ? ? ??? ack data-byte low ?? ?? ?? nak p write to control / test / agc / pll_cap registers (short protocol) s daw wait ack sub-addr ack data-byte high ack data-byte low ack p read from control / test / agc / pll_cap registers (short protocol) s daw wait ack sub-addr ack s dar wait ack data-byte high ??? ??? ack data-byte low ??? ??? nak p note: s = i 2 c-bus start condition from master p = i 2 c-bus stop condition from master daw = device address write dar = device address read ack = acknowledge-bit: low on i2c_da from slave (= mspc, grey) or master (= ccu, hatched) nak = not acknowledge-bit: high on i2c_da from master (= ccu, hatched) to indicate ? end of read ? or from mspc indicating internal error state (not illustrated) wait = i 2 c-clock line held low by the slave (= mspc) while interrupt is serviced (<1.77 ms) fig. 5 ? 1: i 2 c bus protocol i2c_da i2c_cl 1 0 sp (msb first; data must be stable while clock is high) preliminary data sheet msp 3400c 18 micronas i 2 c_cl i 2 c_da as input i 2 c_da as output f im t i2c1 t i2c5 t i2c6 t i2c2 t imol2 t imol1 t i2c4 fig. 5 ? 2: i 2 c bus timing diagram t i2c3 (data: lsb first) 5.2. proposal for msp 3400c i 2 c telegrams 5.2.1. symbols daw device address write dar device address read < start condition > stop condition aa address byte dd data byte 5.2.2. write telegrams msp 3400c preliminary data sheet 19 micronas 5.3. start up sequence after power on or reset, the ic is in an inactive state. the ccu has to transmit the required coefficient set for a given operation via the i 2 c bus. initialization must start with the demodulator part. if required for any reason, the audio processing part can be loaded before the demo- dulator part. the reset pin should not be > 0.45 dvsup (see recom- mended operation conditions) before the 5 volt digital power supply (dvsup) and the analog power supply (avsup) are > 4.75 volt and the msp-clock is running (delay: 2 ms max, 0.5 ms typ.). this means, if the reset low-high edge starts with a delay of 2 ms after dvsup> 4.75 volt and avsup>4.75 volt, even under worst case conditions, the reset is ok. dvsup/v avsup/v time / ms 4.75 oscillator time / ms 0.45 * dvsup min. 2 time / ms resetq max. 2 fig. 5 ? 3: power-up sequence note: the reset should not reach high level be- fore the oscillator has started. this requires a reset delay of >2 ms preliminary data sheet msp 3400c 20 micronas 6. programming the demodulator part 6.1. registers: table and addresses in table 6 ? 1, all write registers are listed. all transmissions on the control bus are 16 bits wide. data for the demodulator part has 8 or 12 significant bits. these data have to be inserted lsb bound and filled with zero bits into the 16 bit transmission word. if chan- nel 1 or channel 2 is selected in the channel matrix while any of the parameters are changed, the corresponding output must be muted. click and crack noise may occur during coefficient changes. table 4 ? 1 explains how to assign fm carriers to the mspc-sound if channels and the corresponding matrix modes in the audio processing part. table 6 ? 1: msp 3400c demodulator write registers register protocol write address (hex) function ad_cv long 00bb input selection, configuration of agc and mute function, and selection of a/d-converter mode_reg long 0083 mode register fir_reg_1 fir_reg_2 long long 0001 0005 serial shift register for 6 ? 8 bit, filter coefficient channel 1 (48 bit) serial shift register for 6 ? 8 bit, + 2 ? 12 bit off set (total 72 bit) dco1_lo dco1_hi dco2_lo dco2_hi long long long long 0093 009b 00a3 00ab increment channel 1 low part increment channel 1 high part increment channel 2 low part increment channel 2 high part pll_cap 1) short 1f switchable pll capacities table 6 ? 2: msp 3400c demodulator read registers register protocol read address (hex) function pll_cap 1) short 1f switchable pll capacities agc_rms 1) short 1e rms value, comparable with reference value c_ad_bits long 0023 a read from this address always responds with 0. this ensures software compatibility with the msp 3410 readout. reading 0 from this register signals ? no nicam ? . 1) the registers pll_cap and agc_rms are only available in msp 3400c. in msp 3410 and msp 34x0d, this register cannot be accessed. msp 3400c preliminary data sheet 21 micronas 6.2. registers: functions and values in the following, the functions of several registers are ex- plained and their (default) values are defined. 6.2.1. setting of parameter ad_cv table 6 ? 3: ad_cv register ad_cv bit range meaning settings ad_cv [0] not used must be set to 0 ad_cv [6:1] reference level in case of automatic gain control = on. constant gain factor when automatic gain control = off . see table 6 ? 5 see table 6 ? 6 ad_cv [7] determination of automatic gain or constant gain 0 = constant gain 1 = automatic gain ad_cv [8] selection of analog input 0 = analog in1 1 = analog in2 ad_cv [9] mspc-carrier-mute function 0 = off: no mute 1 = on: mute (see section 4.1.8.) ad_cv [11 ? 10] programmable carrier-mute level see table 6 ? 4 ad_cv [15 ? 12] not used must be set to 0 table 6 ? 4: carrier mute level step ad_cv [11:10] binary ad_cv [11:10] decimal internal reference level for mute active (dbr: relative to msp 3410 ) 0 1 2 3 00 01 10 11 0 1 2 3 0 dbr ? 3 dbr ? 6 dbr ? 12 dbr table 6 ? 5: reference values ad_cv [6:1] for active agc (ad_cv[7] = 1) application input signal contains ref. value binary ref. value decimal range of input signal at pin ana_in_1+ and ana_in_2+ terrestrial tv 2 fm carriers 101000 40 0.14 ? 3 v pp 1) sat 1 or more fm carriers 100011 35 0.14 ? 3 v pp 1) adr 1 or more fm carriers and 1 or more adr carriers 010100 20 0.14 ? 3 v pp 1) 1) for signals above 1.4 vpp, the minimum gain of 3 db is switched and overflow of the ad converter may result. due to the robustness of the internal processing in fm mode, the ic works properly up to and even more than 3 vpp. in am mode, of course, no ad converter overflow is allowed. as a consequence, in the am-mode, the maximum input at pins 41 or 43 must not exceed 1.4 vpp. preliminary data sheet msp 3400c 22 micronas table 6 ? 6: ad_cv parameters for constant input gain (ad_cv[7]=0) step ad_cv [6:1] constant gain gain input level at pin ana_in1+ and ana_in2+ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 3.00 db 3.85 db 4.70 db 5.55 db 6.40 db 7.25 db 8.10 db 8.95 db 9.80 db 10.65 db 11.50 db 12.35 db 13.20 db 14.05 db 14.90 db 15.75 db 16.60 db 17.45 db 18.30 db 19.15 db 20.00 db maximum input level 1) : 3 v pp (fm) or 1.4 v pp (am) maximum input level: 0.14 v pp 1) 1) for signals above 1.4 vpp, the minimum gain of 3 db is switched and overflow of the ad converter may result. due to the robustness of the internal processing in fm mode, the ic works properly up to and even more than 3 vpp. in am mode, of course, no ad converter overflow is allowed. as a consequence, in the am-mode, the maximum input at pins 41 or 43 must not exceed 1.4 vpp. msp 3400c preliminary data sheet 23 micronas 6.2.2. control register ? mode_reg ? the register ? mode_reg ? contains the control bits de- termining the operation mode of the msp 3400c; table 6 ? 7 explains all bit positions. table 6 ? 7: control word ? mode_reg ? : all bits are ? 0 ? after power-on-reset bit function comment definition recom- mendation [0] dma_sync 1) synchronization to dma 0 : off 1 : on x [1] dctr_tri digital control out 0/1 tristate 0 : active 1 : tristate 0 [2] i2s_tri i 2 s outputs tristate (i2s_cl, i2s_ws, i2s_da_out) 0 : active 1 : tristate 0 [3] i 2 s mode 1) master/slave mode of the i 2 s bus 0 : master 1 : slave x [4] i 2 s_ws mode ws due to the sony or philips-format 0 : sony 1 : philips x [5] audio_cl_out switch audio_clock_output to tristate 0 : on 1 : tristate x [6] not used must be 0 0 [7] fm1 fm2 mspc-channel 1 mode s.table 6 ? 8 [8] am mspc-channel 1/2 mode 0 : fm 1 : am s.table 6 ? 8 [9] hdev high deviation mode (channel matrix must be sound a ) 0 : normal mode 1 : high deviation mode s.table 6 ? 8 [10] not used must be 1 1 [11] s-bus mode 2) mode of pins s_cl and s_id 0 : tristate 1 : active 0 [12] fm2 fir filter gain (fm2 = ch1) see table 6 ? 10 0 : gain = 6 db 1 : gain = 0 db 0 [13] fm2 fir filter coeff. set (fm2 = ch1) see table 6 ? 10 0 : use fir_reg_1 1 : use fir_reg_2 0 [14] adr mode of adr interface 0 : normal mode 1 : adr mode x [15] am-gain additional gain in am-mode 0 : 0 db 1 : +12 db 0 1) in case of synchronization to dma, no i 2 s-slave mode possible. in case of i 2 s-slave mode, no synchronization to dma allowed. i 2 s-slave mode dominates. 2) the normal operation mode is ? tristate ? ; sbus is only used in conjunction with dma. x: depend- ing on mode preliminary data sheet msp 3400c 24 micronas table 6 ? 8: channel modes ? mode_reg [7 ? 9] ? fm1 fm2 bit[7] am bit[8] hdev bit[9] channel 1 channel 2 0 0 0 mute fm-mono (fm1) 1 0 0 fm2 fm1 x 1 0 am am x x 1 fm-mono (high deviation) fm-mono (high deviation) 6.2.3. fir-filter switches to simplify programming of the msp 3400c, two addi- tional switches have been implemented. the fir filter for channel1/fm2 can use either fir_reg_1 coefficients or fir_reg_2 coefficients by means of mode_reg[13]. herewith, it is no longer nec- essary to transmit both coefficient sets in fm-terrestrial mode. the loading sequence for fir_reg_2 is suffi- cient. the additional gain of +6 db in channel1/fm2 can be switched to 0 db by means of mode_reg[12]. togeth- er with mode_reg[13] set to 1, in satellite mode, it is no longer necessary to transmit both fir filter coefficient sets. the loading sequence for fir_reg_2 is sufficient. 6.2.4. fir-parameter the following data values (see table 6 ? 9) are to be transferred 8 bits at a time embedded lsb-bound in a 16 bit word . these sequences must be obeyed. to change a coefficient set, the complete block fir_reg_1 or fir_reg_2 must be transmitted. the new coefficient set will be active without a load_reg rou- tine. table 6 ? 9: loading sequence for fir-coefficients write_adr = fir_reg_1(channel 1: fm2) no. symbol name bits value 1 fm2_coeff. (5) 8 see table 6 ? 10. 2 fm2_coeff. (4) 8 3 fm2_coeff. (3) 8 4 fm2_coeff. (2) 8 5 fm2_coeff. (1) 8 6 fm2_coeff. (0) 8 write_adr = fir_reg_2 (channel 2: fm1/fm mono) no. symbol name bits value 1 * imreg1 (8 lsbs) 8 04 hex 2 * imreg1 / imreg2 (4 msbs / 4 lsbs) 8 40 hex 3 * imreg2 (8 msbs) 8 00 hex 4 fm_coef (5) 8 see table 6 ? 10. 5 fm_coef (4) 8 6 fm_coef (3) 8 7 fm_coef (2) 8 8 fm_coef (1) 8 9 fm_coef (0) 8 * imreg_1/2: two 12-bit off-set constants msp 3400c preliminary data sheet 25 micronas table 6 ? 10: 8-bit fir-coefficients (decimal integer) for msp 3410d; reset status: all coefficients are ? 0 ? coefficients for fir1 0001 hex and fir2 0005 hex terrestrial tv-standards fm - satellite fir filter corresponds to a bandpass with a band- width of b = 130 to 500 khz frequency f c b b/g-,d/k-,m-dual fm 130 khz 180 khz 200 khz 280 khz 380 khz 500 khz autosearch coef(i) fir2 fir2 fir2 fir2 fir2 fir2 fir2 fir2 0 3 73 9 3 ? 8 ? 1 ? 1 75 1 18 53 18 18 ? 8 ? 9 ? 1 19 2 27 64 28 27 4 ? 16 ? 8 36 3 48 119 47 48 6 5 2 35 4 66 101 55 66 78 65 59 39 5 72 127 64 72 107 123 126 40 mode-reg[12] 0 1 1 1 1 1 1 0 mode-reg[13] 1 1 1 1 1 1 1 0 mode_reg[12] should be set to 0 (= 6 db gain) if the level of the fm2-carrier processed in msp-ch1 is appr. 7 db below the fm1- carrier of msp-ch2. if both carriers have the same level, mode_reg[12] must be set to 1 (=0 db gain). mode_reg[13] : if in msp-channel 1 and 2 the same bandwidth is required, it is sufficient to transmit fir_reg2 only and to set mode_reg[13] to 1. for compatibility (besides the above programming), the fir-filter programming as used for the msp 3410b is also possible. adr coefficients are listed in the drp-data sheet. the 130 khz coefficients are based on subcarriers, which are 7 db below an existent main carrier. preliminary data sheet msp 3400c 26 micronas 6.2.5. dco-increments for a chosen tv standard, a corresponding set of 24-bit increments determining the mixing frequencies of the quadrature mixers, has to be written into the ic. in table 6 ? 11, several examples of dco increments are listed. it is necessary to divide them into low part and high part. the formula for the calculation of the increments for any chosen if-frequency is as follows: incr dez = int(f/fs ? 2 24 ) with: int = integer function f = if-frequency in mhz f s = sampling frequency (18.432 mhz) conversion of incr into hex-format and separation of the 12-bit low and high parts lead to the required incre- ments. (dco1_hi or _lo for channel 1, dco2_hi or lo for channel 2). table 6 ? 11: dco increments for the msp 3400c; frequency in mhz, increments in hex frq. mhz dco_hi dco_lo frq. mhz dco_hi dco_lo 4.5 03e8 0000 5.04 5.5 5.58 5.7421875 0460 04c6 04d8 04fc 0000 038e 0000 00aa 5.76 5.85 5.94 0500 0514 0528 0000 0000 0000 6.0 6.2 6.5 6.552 0535 0561 05a4 05b0 0555 0c71 071c 0000 6.6 6.65 6.8 05ba 05c5 05e7 0aaa 0c71 01c7 7.02 0618 0000 7.2 0640 0000 7.38 0668 0000 7.56 0690 0000 msp 3400c preliminary data sheet 27 micronas 6.3. sequences to transmit parameters and to start processing after having been switched on, the mspc must be ini- tialized by transmitting the parameters according to the load_seq_1/2 of table 6 ? 12. in the mspc, the initial- ization sequence must no longer be terminated by trans- mitting load_reg_1/2. the transmitted data are ac- tive as soon as the corresponding i 2 c telegram has finished. therefore, while changing parameters of the demodulator section, a mute is recommended for the af- fected channel (load_seq_1/2: mute all fm, load_seq_1: switch audio processing to chan- nel2/fm1 or mute channel1/fm2). otherwise, distorted sound may occur while switching. for fm-stereo operation, the evaluation of the identifica- tion signal must be performed. for positive identification check, the msp 3400c sound channels have to be switched corresponding to the detected operation mode. 6.4. software proposals for multistandard tv-sets to familiarize the reader with the programming scheme of the msp 3400c, two examples in the shape of flow diagrams are shown in the following sections. 6.4.1. multistandard system b/g german dual fm fig. 6 ? 1 shows a flow diagram for the ccu software, applied for the msp 3400c in a tv set, which facilitates all standards according to system b/g. for the instruc- tions used in the diagram, please refer to table 6 ? 12. after having switched on the tv-set and having initial- ized the msp 3400c (load_seq_1/2), fm-mono sound is available. fig. 6 ? 1 shows how to check for any stereo or bilingual audio information in channel 1. if successful, the msp 3400c must be switched to the desired audio mode. table 6 ? 12: sequences to initialize and start the msp 3400c load_seq_1/2: general initialization 1. ad_cv 2. fir_reg_1 3. fir_reg_2 4. mode_reg 5. dco1_lo 6. dco1_hi 7. dco2_lo 8. dco2_hi fm_ident_check: decoding of the identification signal 1. evaluation of the stereo detection register (dfp register 0018 hex , high part) 2. if necessary, switch the corresponding sound channels within the audio processing part load_seq_1: reinitialization of channel 1 without affecting channel 2 1. fir_reg_1 2. mode_reg 3. dco1_lo 4. dco1_hi (6 ? 8 bit) (12 bit) (12 bit) preliminary data sheet msp 3400c 28 micronas load_seq_1/2 channel 1: fm2 parameter ident_check 0x0018 fig. 6 ? 1: ccu software flow diagram: standard b/g, t = threshold value for stereo/bilingual detection > t > ? t & < t fm_ start channel 2: fm1 parameter pause set fm matrix: to no_matrix set channel matrix: to sound a or b set fm matrix: to no_matrix set channel matrix: to sounda set fm matrix: to g/kmatrix set channel matrix: to stereo audio processing init < ? t bilingual mono stereo fig. 6 ? 2: ccu software flow diagram: sat-mode start load_seq_1/2 msp-channel 1: fm2-parameter msp-channel 2: fm1-parameter stop audio processing init 6.4.2. satellite mode fig. 6 ? 2 shows the simple flow diagram to be used for the msp 3400c in a satellite receiver. for fm-mono operation, the corresponding fm carrier should prefer- ably be processed at the mspc-channel 2 or at the mspc-channel 1 with fir gain = 0 db. 6.4.3. automatic search function for fm-carrier de- tection the am demodulation ability of the msp 3400c offers the possibility to calculate the ? field strength ? of the mo- mentarily selected fm carrier, which can be read out by the ccu. in sat receivers, this feature can be used to make automatic fm carrier search possible. therefore, the mspc has to be switched to am-mode (mode_reg[8]), fm-prescale must be set to 7f hex =+127 dez , and the fm dc notch must be switched off. the sound-if frequency range must now be ? scanned ? in the mspc-channel 2 by means of the pro- grammable quadrature mixer with an appropriate incre- mental frequency (i.e. 10 khz). after each incrementation, a field strength value is avail- able at the quasi-peak detector output (quasi-peak de- tector source must be set to fm), which must be ex- amined for relative maxima by the ccu. this results in either continuing search or switching the msp 3400c back to fm demodulation mode. during the search process, the fir_reg_2 must be loaded with the coefficient set ? autosearch ? , which enables small bandwidth, resulting in appropriate field strength characteristics. the absolute field strength val- ue (can be read out of ? quasi peak detector output fm1 ? ) also gives information on whether a main fm carrier or a subcarrier was detected, and as a practical conse- quence, the fm bandwidth (fir_reg_1/2) and the deemphasis (50 s or adaptive) can be switched auto- matically. due to the fact that a constant demodulation frequency offset of a few khz, leads to a dc-level in the demodu- lated signal, a further fine tuning of the found carrier can be achieved by evaluating the ? dc level readout fm1 ? . therefore, the fm dc notch must be switched on, and the demodulator part must be switched back to fm-de- modulation mode. for a detailed description of the automatic search func- tion, please refer to the corresponding msp 3400c win- dows software. note: the automatic search is still possible by evaluat- ing only the dc level readout fm1 (dc notch on) as it is described with the msp 3410, but the above men- tioned method is faster. 6.4.4. automatic standard detection the am demodulation ability of the msp 3400 c en- ables a simple method of deciding between standard b/g (fm-carrier at 5.5 mhz) and standard i (fm-carrier at 6.0 mhz). it is achieved by tuning the msp 3400c in the am-mode to the two discrete frequencies and eva- luating the field strength via the dc level register or the quasi-peak detector output (mode_reg, dc notch, fm prescale as described in section 6.4.3.). msp 3400c preliminary data sheet 29 micronas 7. programming the audio processing part 7.1. summary of the dsp control registers control registers are 16 bit wide. transmissions via i 2 c bus have to take place in 16 bit words. single data en- tries are 8 bit. some of the defined 16 bit words are di- vided into low and high byte, thus holding two different control entities. all control registers are readable. note: unused parts of the 16 bit registers must be zero. table 7 ? 1: dsp control registers name i 2 c bus address high/ low adjustable range, operational modes reset mode volume loudspeaker channel 0000 hex h [+12 db ... ? 114 db, mute] mute volume / mode loudspeaker channel l 1/8 db steps, reduce volume / tone control 00 hex balance loudspeaker channel [l/r] 0001 hex h [0..100 / 100 % and vv][ ? 127..0 / 0 db and vv] 100%/100% balance mode loudspeaker l [linear mode / logarithmic mode] linear mode bass loudspeaker channel 0002 hex h [+20 db ... ? 12 db] 0 db treble loudspeaker channel 0003 hex h [+15 db ... ? 12 db] 0 db loudness loudspeaker channel 0004 hex h [0 db ... +17 db] 0 db loudness filter characteristic l [normal, super_bass] normal spatial effect strength loudspeaker ch. 0005 hex h [ ? 100%...off...+100%] off spatial effect mode/customize l [sbe, sbe+pse] sbe+pse volume headphone channel 0006 hex h [+12 db ... ? 114 db, mute] mute volume / mode headphone channel l 1/8 db steps, reduce volume / tone control 00 hex volume scart channel 0007 hex h [00 hex ... 7f hex ],[+12 db ... ? 114 db, mute] 00 hex volume / mode scart channel l [linear mode / logarithmic mode] linear mode loudspeaker channel source 0008 hex h [fm, nicam, scart, i 2 s1, i 2 s2] fm loudspeaker channel matrix l [sounda, soundb, stereo, mono...] sounda headphone channel source 0009 hex h [fm, nicam, scart, i 2 s1, i 2 s2] fm headphone channel matrix l [sounda, soundb, stereo, mono...] sounda scart1 channel source 000a hex h [fm, nicam, scart, i 2 s1, i 2 s2] fm scart1 channel matrix l [sounda, soundb, stereo, mono...] sounda i 2 s channel source 000b hex h [fm, nicam, scart, i 2 s1, i 2 s2] fm i 2 s channel matrix l [sounda, soundb, stereo, mono...] sounda quasi-peak detector source 000c hex h [fm, nicam, scart, i 2 s1, i 2 s2] fm quasi-peak detector matrix l [sounda, soundb, stereo, mono...] sounda prescale scart 000d hex h [00 hex ... 7f hex ] 00 hex prescale fm 000e hex h [00 hex ... 7f hex ] 00 hex fm matrix l [no_mat, gstereo, kstereo] no_mat preliminary data sheet msp 3400c 30 micronas reset mode adjustable range, operational modes high/ low i 2 c bus address name deemphasis fm 000f hex h [off, 50 s, 75 s, j17] 50 s adaptive deemphasis fm l [off, wp1] off prescale i 2 s2 0012 hex h [00 hex ... 7f hex ] 10 hex acb register (scart switches and dig_out pins) 0013 hex h/l bits [15..0] 00 hex beeper 0014 hex h/l [00 hex ... 7f hex ]/[00 hex ... 7f hex ] 0/0 identification mode 0015 hex l [b/g, m] b/g prescale i 2 s1 0016 hex h [00 hex ... 7f hex ] 10 hex fm dc notch 0017 hex l [on, off] on mode tone control 0020 hex h [bass/treble, equalizer] bass/treb equalizer loudspeaker ch. band 1 0021 hex h [+12 db ... ? 12 db] 0 db equalizer loudspeaker ch. band 2 0022 hex h [+12 db ... ? 12 db] 0 db equalizer loudspeaker ch. band 3 0023 hex h [+12 db ... ? 12 db] 0 db equalizer loudspeaker ch. band 4 0024 hex h [+12 db ... ? 12 db] 0 db equalizer loudspeaker ch. band 5 0025 hex h [+12 db ... ? 12 db] 0 db automatic volume correction 0029 hex h [off, on, decay time] off volume subwoofer channel 002chex h [0db ... ? 30 db, mute] 0 db subwoofer channel corner frequency 002dhex h [50 hz ... 400 hz] subwoofer: complementary highpass l [off, on] off balance headphone channel [l/r] 0030 hex h [0...100 / 100% and vv][ ? 127...0 / 0 db and vv] 100%/100% balance mode headphone l [linear mode / logarithmic mode] linear mode bass headphone channel 0031 hex h [+20 db ... ? 12 db] 0 db treble headphone channel 0032 hex h [+15 db ... ? 12 db] 0 db loudness headphone channel 0033 hex h [0 db ... +17 db] 0 db loudness filter characteristic l [normal, super_bass] normal note: for compatibility to new technical codes of the msp 3400c, please consider the following compatibility restrictions: if adaptive deemphasis is switched on, 75 s deemphasis must be activated. msp 3400c preliminary data sheet 31 micronas 7.1.1. volume loudspeaker channel and head- phone channel volume loudspeaker 0000 hex 11 msbs volume headphone 0006 hex 11 msbs +12 db 0111 1111 000x 7f0 hex +11.875 db 0111 1110 111x 7ee hex +0.125 db 0111 0011 001x 732 hex 0 db 0111 0011 000x 730 hex ? 0.125 db 0111 0010 111x 72e hex ? 113.875db 0000 0001 001x 012 hex ? 114 db 0000 0001 000x 010 hex mute 0000 0000 xxxx 00x hex reset fast mute 1111 1111 111x ffe hex the highest given positive 11-bit number (7f0 hex ) yields in a maximum possible gain of 12 db. decreasing the volume register by 1 lsb decreases the volume by 0.125 db. volume settings lower than the given mini- mum mute the output. with large scale input signals, positive volume settings may lead to signal clipping. with fast mute, volume is reduced to mute position by digital volume only. analog volume is not changed. this reduces any audible dc plops. going back from fast mute should be done to the volume step before fast mute was activated. clipping mode loudspeaker 0000 hex 3 lsbs clipping mode headphone 0006 hex 3 lsbs reduce volume x000 0 hex reset reduce tone control x001 1 hex compromise mode x010 2 hex if the clipping mode is set to ? reduce volume ? , the fol- lowing clipping procedure is used: to prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer set- ting, the amplification does not exceed 12 db. if the clipping mode is ? reduce tone control ? , the bass or treble value is reduced if amplification exceeds 12 db. if the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume ex- ceeds 12 db. if the clipping mode is ? compromise mode ? , the bass or treble value and volume are reduced half and half if am- plification exceeds 12 db (see example below). if the equalizer is switched on, the gain of those bands is re- duced half and half, where amplification together with volume exceeds 12 db. example: vol.: +6 db bass: +9 db treble: +5 db red. volume 3 9 5 red. tone con. 6 6 5 compromise 4.5 7.5 5 preliminary data sheet msp 3400c 32 micronas 7.1.2. balance loudspeaker and headphone channel positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. in lin- ear mode, a step by 1 lsb decreases or increases the balance by about 0.8% (exact figure: 100/127). in loga- rithmic mode, a step by 1 lsb decreases or increases the balance by 1 db. balance mode loudspeaker 0001 hex lsb balance mode headphone 0030 hex lsb linear xxx0 0 hex reset logarithmic xxx1 1 hex linear mode balance loudspeaker channel [l/r] 0001 hex h balance headphone channel [l/r] 0030 hex h left muted, right 100% 0111 1111 7f hex left 0.8%, right 100% 0111 1110 7e hex left 99.2%, right 100% 0000 0001 01 hex left 100%, right 100% 0000 0000 00 hex reset left 100%, right 99.2% 1111 1111 ff hex left 100%, right 0.8% 1000 0010 82 hex left 100%, right muted 1000 0001 81 hex logarithmic mode balance loudspeaker channel [l/r] 0001 hex h balance headphone channel [l/r] 0030 hex h left ? 127 db, right 0 db 0111 1111 7f hex left ? 126 db, right 0 db 0111 1110 7e hex left ? 1 db, right 0 db 0000 0001 01 hex left 0 db, right 0 db 0000 0000 00 hex reset left 0 db, right ? 1 db 1111 1111 ff hex left 0 db, right ? 127 db 1000 0001 81 hex left 0 db, right ? 128 db 1000 0000 80 hex msp 3400c preliminary data sheet 33 micronas 7.1.3. bass loudspeaker and headphone channel bass loudspeaker 0002 hex h bass headphone 0031 hex h +20 db 0111 1111 7f hex +18 db 0111 1000 78 hex +16 db 0111 0000 70 hex +14 db 0110 1000 68 hex +12 db 0110 0000 60 hex +11 db 0101 1000 58 hex +1 db 0000 1000 08 hex +1/8 db 0000 0001 01 hex 0 db 0000 0000 00 hex reset ? 1/8 db 1111 1111 ff hex ? 1 db 1111 1000 f8 hex ? 11 db 1010 1000 a8 hex ? 12 db 1010 0000 a0 hex with positive bass settings, internal overflow may occur even with overall volume less than 0 db. this will lead to a clipped output signal. therefore, it is not recom- mended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. loudspeaker channel: bass and equalizer cannot work simultaneously (see table: mode tone control). if equalizer is used, bass and treble coefficients must be set to zero and vice versa. 7.1.4. treble l oudspeaker and headphone channel treble loudspeaker 0003 hex h treble headphone 0032 hex h +15 db 0111 1000 78 hex +14 db 0111 0000 70 hex +1 db 0000 1000 08 hex +1/8 db 0000 0001 01 hex 0 db 0000 0000 00 hex reset ? 1/8 db 1111 1111 ff hex ? 1 db 1111 1000 f8 hex ? 11 db 1010 1000 a8 hex ? 12 db 1010 0000 a0 hex with positive treble settings, internal overflow may occur even with overall volume less than 0 db. this will lead to a clipped output signal. therefore, it is not recom- mended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. loudspeaker channel: treble and equalizer cannot work simultaneously (see table: mode tone control). if equalizer is used, bass and treble coefficients must be set to zero and vice versa. preliminary data sheet msp 3400c 34 micronas 7.1.5. loudness loudspeaker and headphone channel loudness loudspeaker 0004 hex h loudness headphone 0033 hex h +17 db 0100 0100 44 hex +16 db 0100 0000 40 hex +1 db 0000 0100 04 hex 0 db 0000 0000 00 hex reset mode loudness loudspeaker 0004 hex l mode loudness headphone 0033 hex l normal (constant volume at 1 khz) 0000 0000 00 hex reset super bass (constant volume at 2 khz) 0000 0100 04 hex loudness increases the volume of low and high frequen- cy signals, while keeping the amplitude of the 1 khz ref- erence frequency constant. the intended loudness has to be set according to the actual volume setting. be- cause loudness introduces gain, it is not recommended to set loudness to a value that ,in conjunction with vol- ume, would result in an overall positive gain. by means of ? mode loudness ? , the corner frequency for bass amplification can be set to two different values. in super bass mode, the corner frequency is shifted up. the point of constant volume is shifted from 1 khz to 2 khz. 7.1.6. spatial effects loudspeaker channel spatial effect strength loudspeaker channel 0005 hex h enlargement 100% 0111 1111 7f hex enlargement 50% 0011 1111 3f hex enlargement 1.5% 0000 0001 01 hex effect off 0000 0000 00 hex reset reduction 1.5% 1111 1111 ff hex reduction 50% 1100 0000 c0 hex reduction 100% 1000 0000 80 hex spatial effect mode 0005 hex [7:4] stereo basewidth en- largement (sbe) and pseudo stereo effect (pse). (mode a) 0000 0 hex reset 0000 0 hex stereo basewidth en- largement (sbe) only. (mode b) 0010 2 hex spatial effect cus- tomize coefficient 0005 hex [3:0] max high pass gain 0000 0 hex reset 2/3 high pass gain 0010 2 hex 1/3 high pass gain 0100 4 hex min high pass gain 0110 6 hex automatic 1000 8 hex there are several spatial effect modes available: mode a (low byte = 00 hex ) is compatible to the formerly used spatial effect. here, the kind of spatial effect de- pends on the source mode. if the incoming signal is in mono mode, pseudo stereo effect is active; for stereo signals, pseudo stereo effect and stereo basewidth enlargement is effective. the strength of the effect is controllable by the upper byte. a negative value reduces the stereo image. a rather strong spatial effect is recom- mended for small tv sets where loudspeaker spacing is rather close. for large screen tv sets, a more moderate spatial effect is recommended. in mode a, even in case of stereo input signals, pseudo stereo effect is active, which reduces the center image. in mode b, only stereo basewidth enlargement is effec- tive. for mono input signals, the pseudo stereo effect has to be switched on. msp 3400c preliminary data sheet 35 micronas it is worth mentioning, that all spatial effects affect ampli- tude and phase response. with the lower 4 bits, the fre- quency response can be customized. a value of 0000 bin yields a flat response for center signals (l = r) but a high pass function of l or r only signals. a value of 0110 bin has a flat response for l or r only signals but a lowpass function for center signals. by using 1000 bin , the fre- quency response is automatically adapted to the sound material by choosing an optimal high pass gain. 7.1.7. volume scart volume mode scart 0007 hex lsb linear xxx0 0 hex reset logarithmic xxx1 1 hex linear mode volume scart 0007 hex h off 0000 0000 00 hex reset 0 db gain (digital full scale (fs) to 2 v rms output) 0100 0000 40 hex +6 db gain ( ? 6 dbfs to 2 v rms output) 0111 1111 7f hex logarithmic mode volume scart 0007 hex 11 msbs +12 db 0111 1111 000x 7f0 hex +11.875 db 0111 1110 111x 7ee hex +0.125 db 0111 0011 001x 732 hex 0 db 0111 0011 000x 730 hex ? 0.125 db 0111 0010 111x 72e hex ? 113.875 db 0000 0001 001x 012 hex ? 114 db 0000 0001 000x 010 hex mute 0000 0000 0000 000 hex reset 7.1.8. channel source modes loudspeaker channel source 0008 hex h headphone channel source 0009 hex h scart channel source 000a hex h i 2 s channel source 000b hex h quasi-peak detector source 000c hex h fm 0000 0000 00 hex reset none (msp3410: nicam) 0000 0001 01 hex scart 0000 0010 02 hex sbus12 0000 0011 03 hex sbus34 0000 0100 04 hex i 2 s1 0000 0101 05 hex i 2 s2 0000 0110 06 hex note: for headphone output it is also possible to select a subwoofer signal derived from the loudspeaker chan- nel. for more details see section 7.1.23. preliminary data sheet msp 3400c 36 micronas 7.1.9. channel matrix modes (see also table 4 ? 1) loudspeaker channel matrix 0008 hex l headphone channel matrix 0009 hex l scart channel matrix 000a hex l i 2 s channel matrix 000b hex l quasi-peak detector- matrix 000c hex l sounda / left / msp-if-channel2 0000 0000 00 hex reset soundb / right / msp-if-channel1 0001 0000 10 hex stereo 0010 0000 20 hex mono 0011 0000 30 hex sum/diff 0100 0000 40 hex ab_xchange 0101 0000 50 hex invert_b 0110 0000 60 hex the sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. if the difference signal on channel b (right) is near to zero, and the sum signal on channel a (left) is high, the incoming audio signal is mono. if there is a significant level on the difference signal, the incoming audio is ste- reo. 7.1.10. scart prescale volume prescale scart 000d hex h off 0000 0000 00 hex reset 0 db gain (2 v rms in- put to digital full scale) 0001 1001 19 hex +14 db gain (400 mv rms input to digital full scale) 0111 1111 7f hex 7.1.11. fm prescale volume prescale fm (normal fm mode) 000e hex h off 0000 0000 00 hex reset maximum volume (28 khz deviation 1) recommended fir- bandwidth: 130 khz) 0111 1111 7f hex deviation 50 khz 1) recommended fir- bandwidth: 200 khz 0100 1000 48 hex deviation 75 khz 1) recommended fir- bandwidth: 200 or 280 khz 0011 0000 30 hex deviation 150 khz 1) recommended fir- bandwidth: 380 khz 0001 1000 18 hex maximum deviation 192 khz 1) recommended fir- bandwidth: 380 khz 0001 0011 13 hex prescale for adaptive deemphasis wp1 recommended fir- bandwidth: 130 khz 0001 0000 10 hex volume prescale fm (high deviation mode) 000e hex h deviation 150 khz 1) recommended fir- bandwidth: 380 khz 0011 0000 30 hex maximum deviation 384 khz 1) recommended fir- bandwidth: 500 khz 0001 0011 13 hex for the high deviation mode, the fm prescaling values can be used in the range between 13 hex to 30 hex . please consider the internal reduction of 6 db for this mode. the fir-bandwidth should be selected to 500 khz. 1) given deviations will result in internal digital full scale signals. appropriate clipping headroom has to be set by the customer. this can be done by decreasing the listed values by a specific factor. msp 3400c preliminary data sheet 37 micronas 7.1.12. fm matrix modes (see also table 4 ? 1) fm matrix 000e hex l no matrix 0000 0000 00 hex reset gstereo 0000 0001 01 hex kstereo 0000 0010 02 hex no_matrix is used for terrestrial mono or satellite ste- reo sound. gstereo dematrixes (l+r, 2r) to (2l, 2r) and is used for german dual carrier stereo system (standard b/g). kstereo dematrixes (l+r, l ? r) to (2l, 2r) and is used for the korean dual carrier stereo system (standard m). 7.1.13. fm fixed deemphasis deemphasis fm 000f hex h 50 s 0000 0000 00 hex reset 75 s 0000 0001 01 hex j17 0000 0100 04 hex off 0011 1111 3f hex 7.1.14. fm adaptive deemphasis fm adaptive deemphasis wp1 000f hex l off 0000 0000 00 hex reset wp1 0011 1111 3f hex must be set to ? off ? in case of dual carrier stereo (ger- man or korean). if ? on ? , fm fixed deemphasis must be set to 75 s. 7.1.15. i 2 s1 and i 2 s2 prescale prescale i 2 s1 0016 hex h prescale i 2 s2 0012 hex h off 00 hex 0 db gain 10 hex reset +18 db gain 7f hex 7.1.16. acb register, definition of the scart- switches and dig_ctr_out pins acb register 0013 hex h dsp in selection of source: sc_1_in mono_in sc_2_in sc_3_in xxxx xx00 reset xxxx xx01 xxxx xx10 xxxx xx11 sc_1_out_l/r selection of source: sc_3_in sc_2_in mono_in da_scart xxxx 00xx reset xxxx 01xx xxxx 10xx xxxx 11xx sc_2_out_l/r selection of source: da_scart sc_1_in mono_in xx00 xxxx reset xx01 xxxx xx10 xxxx dig_ctr_out1 low high x0xx xxxx reset x1xx xxxx dig_ctr_out2 low high 0xxx xxxx reset 1xxx xxxx reset: the reset state is taken at the time of the first write transmission on the control bus to the audio processing part (dsp). by writing to the acb register first, the reset state can be rede- fined. preliminary data sheet msp 3400c 38 micronas 7.1.17. beeper beeper volume 0014 hex h off 0000 0000 00 hex reset maximum volume (full digital scale fds) 0111 1111 7f hex beeper frequency 0014 hex l 16 hz (lowest) 0000 0001 01 hex 1 khz 0100 0000 40 hex 4 khz (highest) 1111 1111 ff hex a squarewave beeper can be added to the loudspeaker channel and the headphone channel. the addition point is just before loudness and volume adjustment. 7.1.18. identification mode identification mode 0015 hex l standard b/g (german stereo) 0000 0000 00 hex reset standard m (korean stereo) 0000 0001 01 hex reset of ident-filter 0011 1111 3f hex to shorten the response time of the identification algo- rithm after a program change between two fm-stereo capable programs, the reset of ident-filter can be ap- plied. sequence: 1. program change 2. reset ident-filter 3. wait at least 1 msec. 4. set identification mode back to standard b/g or m 5. wait approx. 1 sec. 6. read stereo detection register 7.1.19. fm dc notch fm dc notch 0017 hex l on 0000 0000 00 hex reset off 0011 1111 3f hex the dc compensation filter (fm dc notch) for fm input can be switched off. this is used to speed up the auto- matic search function (see sector 6.4.3.). in normal fm- mode, the fm dc notch should be switched on. 7.1.20. mode tone control mode tone control 00020 hex h bass and treble 0000 0000 00 hex reset equalizer 1111 1111 ff hex by means of ? mode tone control ? , bass/treble or equal- izer may be activated. msp 3400c preliminary data sheet 39 micronas 7.1.21. equalizer loudspeaker channel band 1 (below 120 hz) 0021 hex h band 2 (center: 500 hz) 0022 hex h band 3 (center: 1.5 khz) 0023 hex h band 4 (center: 5 khz) 0024 hex h band 5 (above 10khz) 0025 hex h +12 db 0110 0000 60 hex +11 db 0101 1000 58 hex +1 db 0000 1000 08 hex +1/8 db 0000 0001 01 hex 0 db 0000 0000 00 hex reset ? 1/8 db 1111 1111 ff hex ? 1 db 1111 1000 f8 hex ? 11db 1010 1000 a8 hex ? 12 db 1010 0000 a0 hex with positive equalizer settings, internal overflow may occur even with overall volume less than 0 db. this will lead to a clipped output signal. therefore, it is not recom- mended to set equalizer bands to a value that, in con- junction with volume, would result in an overall positive gain. equalizer must not be used simultaneously with bass and treble (mode tone control must be set to ff to use the equalizer). 7.1.22. automatic volume correction (avc) avc on/off 0029hex [15:12] avc off and reset of int. variables 0000 0hex reset avc on 1000 8hex avc decay time 0029hex [11:8] 8 sec (long) 4 sec (middle) 2 sec (short) 20 ms (very short) 1000 8hex 0100 4hex 0010 2hex 0001 1hex different sound sources (e.g. terrestrial channels, sat channels or scart) fairly often don ? t have the same volume level. advertisement during movies as well has mostly a different (higher) volume level, than the movie itself. the automatic volume correction (avc) solves this problem and equalizes the volume levels. the absolute value of the incoming signal is fed into a filter with 16ms attack time and selectable decay time. the decay time must be adjusted as shown in the table above. this attack/decay filter block works similar to a peak hold function. the volume correction value with it ? s quasi continuous step width is calculated using the at- tack/decay filter output. the automatic volume correction works with an internal reference level of ? 18 dbfs. this means, input signals with a volume level of ? 18 dbfs will not be affected by the avc. if the input signals vary in a range of ? 24 db to 0 db the avc compensates this. example: a static input signal of 1 khz on scart has an output level as shown in the table below. scart input 0dbr = 2 vrms volume correc- tion main output 0dbr = 1.4 vrms 0 dbr ? 18 db ? 18 dbr ? 6 dbr ? 12 db ? 18 dbr ? 12 dbr ? 6 db ? 18 dbr ? 18 dbr ? 0 db ? 18 dbr ? 24 dbr + 6 db ? 18 dbr ? 30 dbr + 6 db ? 24 dbr loudspeaker volume = 73h = 0 dbfs scart prescale = 20h i.e. 2.0 vrms = 0dbfs to reset the internal variables, the avc should be switched off and on during any channel or source change. for standard applications, the recommended decay time is 4sec. note: avc should not be used in any dolby prologic modes, except panorama, where no other than the loudspeaker output is active. preliminary data sheet msp 3400c 40 micronas 7.1.23. subwoofer on headphone output the subwoofer channel is created by combining the left and right loudspeaker channels ( (l+r)/2 ) directly be- hind the tone control filter block. a third order lowpass fil- ter with programmable corner frequency and volume ad- justment respectively to the loudspeaker channel output is performed to the bass-signal. additionally, at the loud- speaker channels, a complementary high pass filter can be switched on. the subwoofer channel output can be switched to the headphone d/a converter alternatively with the headphone output. subwoofer channel volume adjust 002chex h 0 db 0000 0000 00hex reset ? 1 db 1111 1111 ffhex ? 29 db 1110 0011 e3hex ? 30 db 1110 0010 e2hex mute 1000 0000 80hex subwoofer channel corner frequency 002dhex h 50 hz .... 400 hz e.g. 50 hz = 5 int 400 hz = 40int 0000 0101 05hex 0010 1000 28hex headphone output 002dhex [7:4] headphone 0000 0hex subwoofer 1000 8hex subwoofer: comple- mentary highpass 002dhex [3:0] hp off 0000 0hex hp on 0001 1hex note: if subwoofer is chosen for headphone output, the corner frequency must be set to the desired value, be- fore the loudspeaker volume is set. this is to avoid plop noise. 7.2. exclusions in general, all functions can be switched independently of the others. one exception exists: 1. if the adaptive deemphasis is activated (reg. 000f hex l), the fm fixed deemphasis (reg. 000f hex h) must be set to 75 s. msp 3400c preliminary data sheet 41 micronas 7.3. summary of readable registers all readable registers are 16 bit wide. transmissions via i 2 c bus have to take place in 16 bit words. single data entries are 8 bit. some of the defined 16 bit words are divided into low and high byte, thus holding two different control entities. these registers are not writeable. name address high/low output range stereo detection register 0018 hex h [80 hex ... 7f hex ] 8 bit two ? s complement quasi peak readout left 0019 hex h&l [00 hex ... 7fff hex ] 16 bit binary quasi peak readout right 001a hex h&l [00 hex ... 7fff hex ] 16 bit binary dc level readout fm1/ch2 ? l 001b hex h&l [00 hex ... 7fff hex ] 16 bit binary dc level readout fm2/ch1 ? r 001c hex h&l [00 hex ... 7fff hex ] 16 bit binary msp hardware version code 001e hex h [00 hex ... ff hex ] msp major revision code l [00 hex ... ff hex ] msp product code 001f hex h [00 hex ... 0a hex ] msp rom version code l [00 hex ... ff hex ] 7.3.1. stereo detection register stereo detection register 0018 hex h stereo mode reading (two ? s complement) mono near zero stereo positive value (ideal reception: 7f hex ) bilingual negative value (ideal reception: 80 hex) 7.3.2. quasi peak detector quasi peak readout left 0019 hex h+l quasi peak readout right 001a hex h+l quasi peak readout [0 hex ... 7fff hex ] values are 16 bit binary the quasi peak readout register can be used to read out the quasi peak level of any input source, in order to ad- just all inputs to the same normalized listening level. the refresh rate is 32 khz. the feature is based on a filter time constant: attack-time: 1.3 ms decay-time: 37 ms preliminary data sheet msp 3400c 42 micronas 7.3.3. dc level register dc level readout fm1 001b hex h+l dc level readout fm2 001c hex h+l dc level [0 hex ... 7fff hex ] values are 16 bit binary the dc level register measures the dc component of the incoming fm signals (fm1 and fm2). this can be used for seek functions in satellite receivers and for if fm frequencies fine tuning. for further processing, the dc content of the demodulated fm signals is sup- pressed. the time constant , defining the transition time of the dc level register, is approximately 28 ms. 7.3.4. msp hardware version code hardware version 001e hex h hardware version [00 hex ... ff hex ] msp 3400c ? c 8 03 hex a change in the hardware version code defines hard- ware optimizations that may have influence on the chip ? s behavior. the readout of this register is identical to the hardware version code in the chip ? s imprint. 7.3.5. msp major revision code major revision 001e hex l msp 3400c 03 hex the msp 3400c is the third generation of ics in the msp family. 7.3.6. msp product code product 001f hex h msp 3400c 0000 0000 00 hex msp 3400 0000 1010 0a hex 1) msp 34 10 0000 1010 0a hex 1) note: the msp 3400 hardware is identical to the msp 3410. therefore, the family code readout will show ? msp 3410 ? instead of its label ? msp 3400 ? . 7.3.7. msp rom version code rom version 001f hex l major software revision [00 hex ... ff hex ] msp 3400c ? b 5 0000 0101 05 hex msp 3400c ? c 6 0000 0110 06 hex msp 3400c ? c 8 0000 1000 08 hex a change in the rom version code defines internal soft- ware optimizations, that may have influence on the chip ? s behavior, e.g. new features may have been in- cluded. while a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new msp 3400c versions ac- cording to this number. the readout of this register is identical to the rom version code in the chip ? s imprint. msp 3400c preliminary data sheet 43 micronas 8. specifications 8.1. outline dimensions 1.2 x 45 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 2 25 +0.25 43 27 25 +0.25 26 10 9 61 9 44 60 1 x 45 0.457 0.2 0.711 1.9 1.5 4.05 0.1 4.75 0.15 1.27 0.1 2.4 2 15 9 1.27 0.1 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 1 +0.2 2.4 fig. 8 ? 1: 68-pin plastic leaded chip carrier package (plcc68) weight approximately 4.8 g dimensions in mm 0.9 23.4 spgs7004-3/4e 0.457 fig. 8 ? 2: 64-pin plastic shrink dual inline package (psdip64) weight approximately 9.0 g dimensions in mm 1.29 132 33 64 3 0.3 1.9 (1) 1.778 0.05 1 0.1 57.7 0.1 3.2 0.4 3.8 0.1 4.8 0.4 19.3 0.1 18 0.1 20.1 0.6 0.27 0.06 spgs0016-4/2e 31 x 1.778 = 55.118 0.1 2.5 0.3 0.24 0.3 14 0.1 1.778 0.05 fig. 8 ? 3: 52-pin plastic shrink dual in line package (psdip52) weight approximately 5.5 g dimensions in mm 126 27 52 0.457 0 ...15 47 0.1 0.4 0.2 4 0.1 3.2 0.2 1 0.1 15.6 0.1 0.27 0.06 25 x 1.778 = 44.47 0.1 spgs0015-1/2e preliminary data sheet msp 3400c 44 micronas 17.2 23.2 8 9.8 1.8 14 20 16 5 8 10.3 23 x 0.8 = 18.4 15 x 0.8 = 12.0 0.8 0.8 41 64 24 1 65 80 40 25 1.28 2.70 1.8 0.1 3 0.2 0.17 0.03 spgs0025-1/1e fig. 8 ? 4: 80-pin plastic quad flat pack package (pqfp80) weight approximately 1.61 g dimensions in mm 8.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram ahvss = connect to ahvss dvss = if not used, connect to dvss ? = pin does not exist in this package pin no. pin name type connection short description plcc 68-pin psdip 64-pin psdip 52-pin pqfp 80-pin 3410d in ( ) (if not used) 1 16 14 9 s_id (adr_ws) out lv sbus ident or adr wordstrobe 1) 2 ? ? ? nc lv not connected 3 15 13 8 s_da_in (adr_da) out lv sbus data input or adr data output 1) 4 14 12 7 i 2 s_da_in1 in lv i 2 s1 data input 5 13 11 6 i 2 s_da_out out lv i 2 s data output 6 12 10 5 i 2 s_ws in/out lv i 2 s wordstrobe 7 11 9 4 i 2 s_cl in/out lv i 2 s clock 8 10 8 3 i 2 c_da in/out x i 2 c data 9 9 7 2 i 2 c_cl in/out x i 2 c clock 10 8 ? 1 nc lv not connected 11 7 6 80 standbyq in x standby (low-active) 12 6 5 79 adr_sel in x i 2 c bus address select 1) depending on mode_reg[14], the sbus interface can be switched into adr_mode with s_cl becoming adr_cl, s_id becoming adr_ws and s_da_in becoming adr_da (see also section 4.5.). 2) due to compatibility with msp 3410, it is possible to connect with dvss as well. msp 3400c preliminary data sheet 45 micronas short description connection type pin name pin no. (if not used) 3410d in ( ) pqfp 80-pin psdip 52-pin psdip 64-pin plcc 68-pin 13 5 4 78 d_ctr_out0 out lv digital control output 0 14 4 3 77 d_ctr_out1 out lv digital control output 1 15 3 ? 76 nc lv not connected 16 2 ? ? nc lv not connected 17 ? ? 75 nc lv not connected 18 1 2 74 aud_cl_out out lv audio clock output 19 64 1 73 dma_sync in lv dma-sync. input 20 63 52 72 xtal_out out x crystal oscillator 21 62 51 71 xtal_in in x crystal oscillator 22 61 50 70 testen in x test pin 23 60 49 69 ana_in2+ in lv if input 2 (if ana_in1+ is used only, connect to avss with 50 pf capaci- tor) 24 59 48 68 ana_in ? in lv if common 25 58 47 67 ana_in1+ in lv if input 1 26 57 46 66 avsup x analog power supply +5 v ? ? ? 65 avsup x analog power supply +5 v ? ? ? 64 nc lv not connected ? ? ? 63 nc lv not connected 27 56 45 62 avss x analog ground ? ? ? 61 avss x analog ground 28 55 44 60 mono_in in lv mono input ? ? ? 59 nc lv not connected 29 54 43 58 vreftop x reference voltage if a/d converter 30 53 42 57 sc1_in_r in lv scart input 1 in, right 31 52 41 56 sc1_in_l in lv scart input 1 in, left 32 51 ? 55 asg1 ahvss analog shield ground 1 33 50 40 54 sc2_in_r in lv scart input 2 in, right 34 49 39 53 sc2_in_l in lv scart input 2 in, left 1) depending on mode_reg[14], the sbus interface can be switched into adr_mode with s_cl becoming adr_cl, s_id becoming adr_ws and s_da_in becoming adr_da (see also section 4.5.). 2) due to compatibility with msp 3410, it is possible to connect with dvss as well. preliminary data sheet msp 3400c 46 micronas short description connection type pin name pin no. (if not used) 3410d in ( ) pqfp 80-pin psdip 52-pin psdip 64-pin plcc 68-pin 35 48 ? 52 asg2 ahvss analog shield ground 2 36 47 38 51 sc3_in_r in lv scart input 3 in, right 37 46 37 50 sc3_in_l in lv scart input 3 in, left 38 45 ? 49 nc (asg4) lv not connected 39 44 ? 48 nc (sc4_in_r) lv not connected 40 43 ? 47 nc (sc4_in_l) lv not connected 41 ? ? 46 nc lv or ahvss not connected 42 42 36 45 agndc x analog reference voltage high voltage part 43 41 35 44 ahvss x analog ground ? ? ? 43 ahvss x analog ground ? ? ? 42 nc lv not connected ? ? ? 41 nc lv not connected 44 40 34 40 capl_m x volume capacitor main 45 39 33 39 ahvsup x analog power supply 8.0 v 46 38 32 38 capl_a x volume capacitor aux 47 37 31 37 sc1_out_l out lv scart output 1, left 48 36 30 36 sc1_out_r out lv scart output 1, right 49 35 29 35 vref1 x reference ground 1 high voltage part 50 34 28 34 sc2_out_l out lv scart output 2, left 51 33 27 33 sc2_out_r out lv scart output 2, right 52 ? ? 32 asg3 ahvss 2) analog shield ground 3 53 32 ? 31 nc lv not connected 54 31 26 30 nc (dacm_sub) lv not connected 55 30 ? 29 nc lv not connected 56 29 25 28 dacm_l out lv analog output main, left 1) depending on mode_reg[14], the sbus interface can be switched into adr_mode with s_cl becoming adr_cl, s_id becoming adr_ws and s_da_in becoming adr_da (see also section 4.5.). 2) due to compatibility with msp 3410, it is possible to connect with dvss as well. msp 3400c preliminary data sheet 47 micronas short description connection type pin name pin no. (if not used) 3410d in ( ) pqfp 80-pin psdip 52-pin psdip 64-pin plcc 68-pin 57 28 24 27 dacm_r out lv analog output main, right 58 27 23 26 vref2 x reference ground 2 high voltage part 59 26 22 25 daca_l out lv analog output aux, left 60 25 21 24 daca_r out lv analog output aux, right ? ? ? 23 nc lv not connected ? ? ? 22 nc lv not connected 61 24 20 21 resetq in x power-on-reset 62 23 ? 20 nc lv not connected 63 22 ? 19 nc lv not connected 64 21 19 18 nc lv not connected 65 20 18 17 i 2 s_da_in2 in lv i 2 s2-data input 66 19 17 16 dvss x digital ground ? ? ? 15 dvss x digital ground ? ? ? 14 dvss x digital ground 67 18 16 13 dvsup x digital power supply +5 v ? ? ? 12 dvsup x digital power supply +5 v ? ? ? 11 dvsup x digital power supply +5 v 68 17 15 10 s_cl (adr_cl) out lv sbus clock or adr clock 1) 1) depending on mode_reg[14], the sbus interface can be switched into adr_mode with s_cl becoming adr_cl, s_id becoming adr_ws and s_da_in becoming adr_da (see also section 4.5.). 2) due to compatibility with msp 3410, it is possible to connect with dvss as well. preliminary data sheet msp 3400c 48 micronas 8.3. pin configurations 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 654321 44 43 42 41 40 68 67 66 65 64 63 62 61 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 s_id nc s_da_in i2s_da_in1 i2s_da_out i2s_ws i2c_da i2s_cl i2c_cl nc standbyq adr_sel d_ctr_out0 d_ctr_out1 nc nc nc aud_cl_out dma_sync xtal_out xtal_in testen ana_in2+ ana_in ? ana_in1+ avsup avss mono_in vreftop sc1_in_r sc1_in_l asg1 sc2_in_r sc2_in_l asg2 sc3_in_r sc3_in_l nc nc nc nc agndc ahvss capl_m ahvsup capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r asg3 nc nc nc dacm_l dacm_r vref2 daca_l daca_r resetq nc nc nc i2s_da_in2 dvss dvsup s_cl msp 3400c fig. 8 ? 5: 68-pin plcc package msp 3400c preliminary data sheet 49 micronas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 aud_cl_out nc nc d_ctr_out0 adr_sel standbyq nc i2c_cl i2c_da i2s_cl i2s_ws i2s_da_in1 s_da_in s_id s_cl dvsup dvss i2s_da_in2 nc testen ana_in1+ avsup avss vreftop sc1_in_l sc1_in_r i2s_da_out sc3_in_l sc3_in_r asg2 sc2_in_r xtal_in xtal_out mono_in d_ctr_out1 sc2_in_l asg1 ana_in ? ana_in2+ dma_sync 21 22 23 24 25 26 27 28 29 30 31 32 nc nc daca_r daca_l vref2 dacm_r dacm_l asg3 nc nc resetq nc 33 34 35 36 37 38 39 40 41 42 43 44 ahvss capl_a sc1_out_l sc1_out_r sc2_out_l sc2_out_r agndc nc vref1 ahvsup capl_m nc msp 3400c fig. 8 ? 6: 64-pin shrink psdip package fig. 8 ? 7: 52-pin shrink psdip package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 d_ctr_out0 adr_sel standbyq i2c_cl i2c_da i2s_cl i2s_ws i2s_da_in1 s_da_in s_id s_cl dvsup dvss i2s_da_in2 testen ana_in1+ avsup avss vreftop sc1_in_l sc1_in_r i2s_da_out sc3_in_l sc3_in_r sc2_in_r xtal_in xtal_out mono_in d_ctr_out1 sc2_in_l ana_in ? ana_in2+ 21 22 23 24 25 26 daca_l vref2 dacm_r dacm_l nc daca_r 27 28 29 30 31 32 ahvss capl_a sc1_out_l sc1_out_r sc2_out_l sc2_out_r agndc vref1 ahvsup capl_m msp 3400c aud_cl_out resetq nc nc preliminary data sheet msp 3400c 50 micronas 62 63 64 65 66 67 68 69 70 71 72 345678910111213 73 74 75 76 77 78 79 80 12 61 60 59 58 57 56 17 16 15 14 55 54 53 52 51 50 49 48 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 sc1_in_r vreftop nc mono_in avss nc avss nc avsup avsup ana_in1+ ana_in ? ana_in2+ testen xtal_out xtal_in dma_sync aud_cl_out nc nc d_ctr_out1 d_ctr_out0 adr_sel standby_q nc i2c_cl i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 s_da_in i2s_da_in2 nc nc nc resetq nc nc daca_r daca_l vref2 dacm_r dacm_l nc nc nc asg3 sc2_out_r sc2_out_l vref1 sc1_out_r sc1_out_l capl_a ahvsup capl_m nc nc ahvss ahvss agndc nc nc nc msp 3400c 47 46 45 44 43 42 41 18 19 20 21 22 23 24 sc2_in_l sc2_in_r asg1 sc1_in_l nc sc3_in_l sc3_in_r asg2 dvsup dvss dvss dvss s_id s_cl dvsup dvsup fig. 8 ? 8: 80-pin pqfp package msp 3400c preliminary data sheet 51 micronas 8.4. pin circuits fig. 8 ? 9: output pins 1, 5, 13, 14, and 68 (s_id, i 2 s_da_out, d_ctr_out0/1, s_cl) p dv sup n gnd p dv sup n gnd fig. 8 ? 10: input pins 4 and 65 (i 2 s_da_in1/2) fig. 8 ? 11: input/output pins 8 and 9 (i 2 c_da, i 2 c_cl) n gnd fig. 8 ? 12: input pins 11, 12, 61, and 62 (standbyq, adr_sel, resetq, testen) fig. 8 ? 13: input/output pins 6 and 7 (i 2 s_ws, i 2 s_cl) p dv sup n gnd fig. 8 ? 14: input pin 19 (dma_sync) 2.5 v fig. 8 ? 15: input pin 3 (s_da_in) p dv sup n gnd fig. 8 ? 16: output/input pins 18, 20, and 21 (aud_cl_out, xtalin/out) 2.5 v p n 500 k 3 ? 30 pf 3 ? 30 pf fig. 8 ? 17: input pins 23 ? 25 and 29 (ana_in2+, ana_in ? , ana_in1+, vreftop) d a anain1+ anain2+ anain ? vreftop preliminary data sheet msp 3400c 52 micronas fig. 8 ? 18: input pin 28 (mono_in) 16 k 3.75 v fig. 8 ? 19: capacitor pins 44 and 46 (capl_m, capl_a) 0...2 v fig. 8 ? 20: input pins 30, 31, 33, 34, 36, and 37 (sc1 ? 3_in_l/r) 40 k 3.75 v fig. 8 ? 21: output pins 56, 57, 59, and 60 (daca_l/r, dacm_l/r) 3.3 k 0...1.2 ma ahv sup fig. 8 ? 22: pin 42 (agndc) 125 k 3.75 v fig. 8 ? 23: output pins 47, 48, 50 and 51 (sc_1/2_out_l/r) 300 40 pf 80 k 3.75 v msp 3400c preliminary data sheet 53 micronas 8.5. electrical characteristics 8.5.1. absolute maximum ratings symbol parameter pin name min. max. unit t a ambient operating temperature ? 0 70 c t s storage temperature ? ? 40 125 c v sup1 first supply voltage ahvsup ? 0.3 9.0 v v sup2 second supply voltage dvsup ? 0.3 6.0 v v sup3 third supply voltage avsup ? 0.3 6.0 v dv sup23 voltage between avsup and dvsup avsup, dvsup ? 0.5 0.5 v p tot chip power dissipation plcc68 without heat spreader ahvsup, dvsup, avsup 1100 mw v idig input voltage, all digital inputs ? 0.3 v sup2 +0.3 v i idig input current, all digital pins ? ? 20 +20 ma 1) v iana input voltage, all analog inputs scn_in_s, 2) mono_in ? 0.3 v sup1 +0.3 v i iana input current, all analog inputs scn_in_s, 2) mono_in ? 5 +5 ma 1) i oana output current, all scart outputs scn_out_s 2) 3) , 4) 3) , 4) i oana output current, all analog outputs except scart outputs dacp_s 2) 3) 3) i cana output current, other pins connected to capacitors capl_p, 2) agndc 3) 3) 1) positive value means current flowing into the circuit 2) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? 3) the analog outputs are short circuit proof with respect to first supply voltage and ground. 4) total chip power dissipation must not exceed absolute maximum rating. stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. preliminary data sheet msp 3400c 54 micronas 8.5.2. recommended operating conditions (at t a = 0 to 70 c) symbol parameter pin name min. typ. max. unit v sup1 first supply voltage ahvsup 7.6 8.0 8.4 v v sup2 second supply voltage dvsup 4.75 5.0 5.25 v v sup3 third supply voltage avsup 4.75 5.0 5.25 v v reil reset input low voltage resetq 0.45 v sup2 v reih reset input high voltage 0.8 v sup2 t reil reset low time after dvsup stable and oscillator startup 5 s v dmail sync input low voltage dma_sync 0.44 v sup1 v dmaih sync input high voltage 0.56 v sup1 t dma sync input frequency 18.0 khz r dma sync input clock high-level time 500 ns v digil digital input low voltage standbyq, adr sel 0.25 v sup2 v digih digital input high voltage adr _ sel , testen 0.75 v sup2 t stbyq1 standbyq setup time before turn-off of second supply voltage standbyq, dvsup 1 s i 2 c-bus recommendations v imil i 2 c-bus input low voltage i 2 c_cl, i 2 cda 0.3 v sup2 v imih i 2 c-bus input high voltage i 2 c _ da 0.6 v sup2 f im i 2 c-bus frequency i 2 c_cl 1.0 mhz t i2c1 i 2 c start condition setup time i 2 c_cl, i 2 cda 120 ns t i2c2 i 2 c stop condition setup time i 2 c _ da 120 ns t i2c3 i 2 c-clock low pulse time i 2 c_cl 500 ns t i2c4 i 2 c-clock high pulse time 500 ns t i2c5 i 2 c-data setup time before rising edge of clock i 2 c_cl, i 2 c_da 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns v i2sil i 2 s-data input low voltage i2s_da_in1/2 0.25 v sup2 v i2sih i 2 s-data input high voltage 0.75 v sup2 msp 3400c preliminary data sheet 55 micronas unit max. typ. min. pin name parameter symbol t i2s1 i 2 s-data input setup time before rising edge of clock i2s_da_in1/2, i2s_cl 20 ns t i2s2 i 2 s-data input hold time after falling edge of clock 0 ns v i2sidl i 2 s-input low voltage when msp 3400c in i2s-slave-mode i2s_cl, i2s_ws 0.25 v sup2 v i2sidh i 2 s-input high voltage when msp 3400c in i2s-slave-mode 0.75 v sup2 f i2scl i 2 s-clock input frequency when msp 3400c in i2s-slave-mode i2s_cl 1.024 mhz r i2scl i 2 s-clock input ratio when msp 3400c in i2s-slave-mode 0.9 1.1 f i2sws i 2 s-wordstrobe input frequency when msp 3400c in i2s-slave- mode i2s_ws 32.0 khz t i2sws1 i 2 s-wordstrobe input setup time before rising edge of clock when msp 3400c in i2s-slave-mode i2s_ws, i2s_cl 60 ns t i2sws2 i 2 s-wordstrobe input hold time after falling edge of clock when msp 3400c in i2s-slave-mode 0 ns v sbusil sbus-data input low voltage s_da_in 0.6 v i sbusil sbus-data input low current 0.9 1.7 3.2 ma v sbustrig sbus-data input trigger voltage 0.8 1.2 v t sbus1 sbus-data input setup time before rising edge of clock s_da_in, s_cl 10 ns t sbus2 sbus-data input hold time after falling edge of clock 0 ns crystal recommendations for master-slave application f p parallel resonance frequency at 12 pf load capacitance 18.432 mhz f tol accuracy of adjustment ? 20 +20 ppm d tem frequency variation versus temperature ? 20 +20 ppm r r series resistance 8 25 ? c 0 shunt (parallel) capacitance 6.2 7.0 pf c 1 motional (dynamic) capacitance 19 24 ff preliminary data sheet msp 3400c 56 micronas unit max. typ. min. pin name parameter symbol load capacitance recommendations for master-slave applications c l external load capacitance 2) xtal_in, xtal_out psdip 1.5 plcc 3.3 pf pf f cl required open loop clock frequency (t amb = 25 c) 18.431 18.433 mhz crystal recommendations for fm application (no master-slave mode possible) f p parallel resonance frequency at 12 pf load capacitance 18.432 mhz f tol accuracy of adjustment ? 100 +100 ppm d tem frequency variation versus temperature ? 50 +50 ppm r r series resistance 8 25 ? c 0 shunt (parallel) capacitance 6.2 7.0 pf load capacitance recommendations for fm application (no master-slave mode possible) c l external load capacitance 2) xtal_in, xtal_out psdip 1.5 plcc 3.3 pf pf amplitude recommendation for operation with external clock input (c load after reset = 22 pf) v xca external clock amplitude xtal_in 0.7 v pp analog input and output recommendations c agndc agndc-filter-capacitor agndc ? 20% 3.3 f ceramic capacitor in parallel ? 20% 100 nf c insc dc-decoupling capacitor in front of scart inputs scn_in_s 1) ? 20% 330 +20% nf v insc scart input level 2.0 v rms v inmono input level, mono input mono_in 2.0 v rms r lsc scart load resistance scn_out_s 1) 10 k ? c lsc scart load capacitance 6.0 nf c vma main/aux volume capacitor capl_m, capl_a 10 f c fma main/aux filter capacitor dacm_s, daca_s 1) ? 10% 1 +10% nf 1) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? 2) external capacitors at each crystal pin to ground are required. they are necessary to tune the open-loop fre- quency of the internal pll and to stabilize the frequency in closed-loop operation. the higher the capacitors, the lower the clock frequency results. the nominal free running frequency should match 18.432 mhz as closely as possible. due to different layouts of customer pcbs, the matching capacitor size should be defined in the application. the suggested values (1.5 pf/3.3 pf) are figures based on experience with various pcb layouts. msp 3400c preliminary data sheet 57 micronas unit max. typ. min. pin name parameter symbol recommendations for analog sound if input signal c vreftop vreftop-filter-capacitor vreftop ? 20% 10 f ceramic capacitor in parallel ? 20% 100 nf v if analog input range (complete sound if, 0 ? 9 mhz) ana_in1+, ana_in2+, ana in 0.14 0.8 3 vpp r fm ratio: fm-main/fm-sub satellite ana _ in ? 7 db r fm1/fm2 ratio: fm1/fm2 german fm-system 7 db r fc ratio: main fm carrier/color carrier 15 ? ? db r fv ratio: main fm carrier/luma components 15 ? ? db pr if passband ripple ? ? 2 db db sup hf suppression of spectrum above 9.0 mhz 15 ? db fm max maximum fm-deviation (apprx.) normal mode high deviation mode 192 360 khz preliminary data sheet msp 3400c 58 micronas 8.5.3. characteristics at t a = 0 to 70 c, f clock = 18.432 mhz (typical values are measured at t a = 25 c, ahvsup = 8 v, dvsup = 5 v, avsup = 5 v.) symbol parameter pin name min. typ. max. unit test conditions dco f clock clock input frequency xtal_in 18.432 mhz d clock clock high to low ratio 45 55 % t jitter clock jitter (verification not provided in production test) 50 ps v xtaldc dc-voltage oscillator 2.5 v t startup oscillator startup time at vdd slew-rate of 1 v / 1 s xtal_in, xtal_out 0.4 2.0 ms power supply i sup1a first supply current (active) analog volume for main and aux at 0db analog volume for main and aux at ? 30db at t j = 27 c ahvsup 8.2 5.6 14.8 10.0 22.0 15.0 ma ma f = 18.432 mhz ahvsup = 8 v dvsup = 5 v avsup = 5 v i sup2a second supply current (active) dvsup 60 65 70 ma f = 18.432 mhz dvsup = 5 v i sup3a third supply current (active) avsup 25 ma f = 18.432 mhz avsup = 5 v i sup1s first supply current (standby mode) at t j = 27 c ahvsup 2.8 5.0 7.2 ma standbyq = low vsup = 8 v audio clock output v apuac audio clock output ac voltage aud_cl_out 1.2 v pp 40 pf load v apudc audio clock output dc voltage 0.4 0.6 v sup1 digital output v dctrol digital output low voltage d_ctr_out0 d ctr out1 0.4 v i ddctr = 1 ma v dctroh digital output high voltage d _ ctr _ out1 4.0 v i ddctr = ? 1 ma i 2 c bus v imol i 2 c-data output low voltage i 2 c_da 0.4 v i imol = 3 ma i imoh i 2 c-data output high current 1 a v imoh = 5 v t imol1 i 2 c-data output hold time after falling edge of clock i 2 c_da, i 2 c_cl 15 ns t imol2 i 2 c-data output setup time before rising edge of clock 100 ns f im = 1 mhz dvsup = 5 v sbus f sb sbus-clock frequency s_cl 4608 khz dvsup = 5 v t s1/s2 sbus-clock high/low-ratio 0.9 1.0 1.1 ns t s3 sbus setup time before ident end pulse s_cl, s_id 210 ns dvsup = 5.25 v f sio sbus ident frequency s_id 32 khz t s6 sbus-ident end pulse time 210 ns dvsup = 5.25 v msp 3400c preliminary data sheet 59 micronas test conditions unit max. typ. min. pin name parameter symbol i 2 s bus v i2sol i 2 s output low voltage i2s_ws, i2s cl 0.4 v i i2sol = 1 ma v i2soh i 2 s output high voltage i2s _ cl , i2s_da_out 4.0 v i i2soh = ? 1 ma f i2scl i 2 s-clock output frequency i2s_cl 1204 khz dvsup = 5 v f i2sws i 2 s-wordstrobe output frequency i2s_ws 32.0 khz dvsup = 5 v t i2s1/i2s2 i 2 s-clock high/low-ratio i2s_cl 0.9 1.0 1.1 t i2s3 i 2 s-data setup time before rising edge of clock i2s_cl, i2s_da_out 200 ns dvsup = 4.75 v t i2s4 i 2 s-data hold time after falling edge of clock 12 ns dvsup = 5.25 v t i2s5 i 2 s-wordstrobe setup time before rising edge of clock i2s_cl, i2s_ws 100 ns dvsup = 4.75 v t i2s6 i 2 s-wordstrobe hold time after falling edge of clock 50 ns dvsup = 5.25 v analog ground v agndc0 agndc open circuit voltage agndc 3.64 3.73 3.84 v r load 10 m ? r outagn agndc output resistance at t j = 27 c from t a = 0 to 70 c 70 70 125 180 180 k ? k ? 3 v v agndc 4 v analog input resistance r insc scart input resistance at t j = 27 c from t a = 0 to 70 c scn_in_s 1) 25 25 40 58 58 k ? k ? f signal = 1 khz, i 0.05 ma r inmono mono input resistance at t j = 27 c from t a = 0 to 70 c mono_in 10 10 16 23 23 k ? k ? f signal = 1 khz, i 0.1 ma audio analog-to-digital-converter v aicl analog input clipping level for analog-to-digital-conversion scn_in_s, 1) mono_in 2.02 2.12 2.22 v rms f signal = 1 khz scart outputs r outsc scart output resistance at t j = 27 c from t a = 0 to 70 c scn_out_s 1) 0.20 0.20 0.33 0.46 0.5 k ? k ? f signal = 1 khz, i = 0.1 ma dv outsc deviation of dc-level at scart output from agndc voltage ? 70 +70 mv a sctosc gain from analog input to scart output scn_in_s 1) mono_in ? 1.0 0 +0.5 db f signal = 1khz f rsctosc frequency response from analog input to scart output bandwidth: 0 to 20000 hz ? 0.5 0 +0.5 db with respect to 1 khz v outsc signal level at scart-output during full-scale digital input signal from dsp scn_out_s 1) 1.8 1.9 2.0 v rms f signal = 1 khz 1) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? preliminary data sheet msp 3400c 60 micronas test conditions unit max. typ. min. pin name parameter symbol main and aux outputs r outma main/aux output resistance at t j = 27 c from t a = 0 to 70 c dacp_s 1) 2.1 2.1 3.3 4.6 5.0 k ? k ? f signal = 1 khz, i = 0.1 ma v outdcma dc-level at main/aux-output for analog volume at 0 db for analog volume at ? 30 db 1.74 ? 1.94 61 2.14 ? v mv v outma signal level at main/aux-output during full-scale digital input signal from dsp for analog volume at 0 db 1.23 1.37 1.51 v rms f signal = 1 khz analog performance snr signal-to-noise ratio from analog input to dsp mono_in, scn_in_s 1) 85 88 db input level = ? 20 db with resp. to v aicl , f sig = 1 khz, equally weighted 20 hz ... 16 khz 2) from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 93 96 db input level = ? 20 db, f sig = 1 khz, equally weighted 20 hz ... 20 khz from dsp to scart output scn_out_s 1) 85 88 db input level = ? 20 db, f sig = 1 khz, equally weighted 20 hz ... 15 khz 3) from dsp to main/aux-output for analog volume at 0 db for analog volume at ? 30 db dacp_s 1) 85 78 88 83 db db input level = ? 20 db, f sig = 1 khz, equally weighted 20 hz ... 15 khz 3) thd total harmonic distortion from analog input to dsp mono_in, scn_in_s 1) 0.05 % input level = ? 3 dbr with resp. to v aicl , f sig =1khz, equally weighted 20 hz ...16 khz, r load = 30 k ? 2) from analog input to scart output mono_in, scn_in_s scn_out_s 1) 0.01 0.03 % input level = ? 3 dbr, f sig = 1 khz, equally weighted 20 hz ... 20 khz, r load = 30 k ? from dsp to scart output scn_out_s 1) 0.01 0.03 % input level = ? 3 dbr, f sig = 1 khz, equally weighted 20 hz ... 16 khz, r load = 30 k ? 3) from dsp to main or aux output daca_s, dacm_s 1) 0.01 0.03 % input level = ? 3 dbr, f sig = 1 khz, equally weighted 20 hz ... 16 khz, r load = 30 k ? 3) 1) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? 2) dsp measured at i 2 s-output 3) dsp input at i 2 s-input msp 3400c preliminary data sheet 61 micronas test conditions unit max. typ. min. pin name parameter symbol xtalk crosstalk attenuation ? plcc68 ? psdip64 input level = ? 3 db, f sig = 1 khz, unused ana- log inputs connected to ground by z<1 k ? between left and right channel within scart input/out- put pair (l r, r l) equally weighted 20 hz ... 20 khz scn_in scn_out 1) plcc68 psdip64 80 80 db db 2) scn_in dsp 1) plcc68 psdip64 80 80 db db dsp scn_out 1) plcc68 psdip64 80 80 db db 3) between left and right channel within main or aux output pair equally weighted 20 hz ... 16 khz dsp dacp 1) plcc68 psdip64 80 75 db db 3) between scart input/output pairs 1) (equally weighted 20 hz 20 khz) d = disturbing program o = observed program 20 hz ... 20 khz) same signal source on left and right disturbing channel effect on each d: mono/scn_in scn_out plcc68 o: mono/scn_in scn_out 1) psdip64 100 100 db db channel , effect on each observed output channel d: mono/scn_in scn_out plcc68 o: or unsel. mono/scn_in dsp 1) psdip64 95 95 db db 2) d: mono/scn_in sc1_out plcc68 o: dsp scn_out 1) psdip64 100 100 db db 3) d: mono/scn_in unselected plcc68 o: dsp sc1_out 1) psdip64 100 100 db db 3) crosstalk between main and aux output pairs dsp dacp 1) plcc68 psdip64 95 90 db db (equally weighted 20 hz ... 16 khz) 3) same signal source on left and right disturbing channel, effect on each observed output channel crosstalk from main or aux output to scart output and vice versa (equally weighted 20 hz ... 20 khz) same signal source on d = disturbing program o = observed program g left and right disturbing channel, effect on each observed output channel d: mono/scn_in/dsp scn_out plcc68 o: dsp dacp 1) psdip64 90 85 db db scart output load resis- tance 10 k ? d: mono/scn_in/dsp scn_out plcc68 o: dsp dacp 1) psdip64 95 85 db db scart output load resis- tance 30 k ? d: dsp dacp plcc68 o: mono/scn_in scn_out 1) psdip64 100 95 db db 3) d: dsp dacp plcc68 o: dsp scn_out 1) psdip64 100 95 db db 1) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? 2) dsp measured at i 2 s-output 3) dsp input at i 2 s-input preliminary data sheet msp 3400c 62 micronas test conditions unit max. typ. min. pin name parameter symbol psrr: rejection of noise on ahvsup at 1 khz psrr agndc agndc 80 db from analog input to dsp mono_in scn_in_s 1) 69 db from analog input to scart output mono_in scn_in_s, 1) scn_out_s 1) 74 db from dsp to scart output scn_out_s 1) 70 db from dsp to main/aux output dacp_s 1) 80 db sound if input section dc vreftop dc voltage at vreftop vreftop 2.4 2.6 2.7 v v supanalog = 5 v r load 10 m ? r ifin input impedance ana_in1+, ana_in2+, ana_in ? 1.5 10.5 2 14.1 2.5 17.6 kohm agc = +20 db agc = +3 db r load 10 m ? dc ana_in dc voltage on if inputs 1.3 1.5 1.7 v avsup = 5 v r load 10 m ? xtalk if crosstalk attenuation 40 t.b.d. ? db f sig = 1 mhz, input level = ? 2 dbr bw if 3 db bandwidth 10 ? ? mhz input level = ? 2 dbr agc agc step width t.b.d. 0.85 t.b.d. db f sig = 1 mhz, input level = ? 2 dbr 1) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? msp 3400c preliminary data sheet 63 micronas test conditions unit max. typ. min. pin name parameter symbol overall performance s/n fm fm input to main/aux/scart output dacp_s, scn_out_s 1) 70 ? db 1 fm-carrier 5.5 mhz, 50 s, 1 khz, 40 khz de- viation; rms, unweighted 0 to 15 khz; full input range s/n d2mac signal to noise ratio of d2mac baseband signal on main/aux/ scart outputs tbd ? db thd fm total harmonic distortion + noise of fm demodulated signal on main/aux/scart output ? 0.3 % 1 fm-carrier 5.5 mhz, 1khz, 50 s; 40 khz devi- ation; full input range thd d2mac total harmonic distortion + noise of d2mac baseband signal for main/aux/scart output ? 0.01 0.1 % 2.12 khz, modulator input level = 0 dbref dv fmout tolerance of output voltage of fm demodulated signal ? 1.5 +1.5 db 1 fm-carrier, 50 s, 1 khz 40 khz deviation; rms dv- d2macout tolerance of output voltage of d2mac baseband signal ? 1.5 +1.5 db 2.12 khz, modulator input level = 0 dbref fr fm fm frequency response on main/ aux/scart outputs, bandwidth 20 to 15000 hz ? 1.0 +1.0 db 1 fm-carrier 5.5 mhz, 50 s, modulator input level = ? 14.6 dbref; rms fr d2mac d2mac frequency response on main/aux/scart outputs, band- width 20 to 15000 hz ? 1.0 +1.0 db modulator input level = ? 12 db dbref; rms sep fm fm channel separation (stereo) 50 db 2 fm-carriers 5.5/5.74 mhz, 50 s, 1 khz, 40 khz deviation; rms sep d2mac d2mac channel separation (stereo) 80 db xtalk fm fm crosstalk attenuation (dual) 80 db 2 fm-carriers 5.5/5.74 mhz, 50 s, 1 khz, 40 khz deviation; rms xtalk- d2mac d2mac crosstalk attenuation (dual) 80 db 1) ? n ? means ? 1 ? , ? 2 ? or ? 3 ? , ? s ? means ? l ? or ? r ? , ? p ? means ? m ? or ? a ? preliminary data sheet msp 3400c 64 micronas 9. application of the msp 3400c 10 f 330 nf if 2 in signal gnd if 1 in 18.432 mhz 28 (55) mono_in main head- phone msp 3400c 11 (7) standby q tuner 2 tuner 1 +8.0 v 1 f dacm_l (29) 56 dacm_r (28) 57 daca_l (26) 59 30 (53) sc1_in_r 31 (52) sc1_in_l 33 (50) sc2_in_r 34 (49) sc2_in_l 52 (30) asg3 d_ctr_out1 (4) 14 9 (9) i 2 c-cl 1 (16) s_id 5v 5v 8.0 v 68 (17) s_cl capl_m (40) 44 capl_a (46) 38 5 (13) i 2 s_da_out 65 (20) i 2 s_da_in2 45 (39) ahvsup 43 (41) ahvss 26 (57) avsup 67 (18) dvsup 66 (19) dvss 61 (24) resetq 32 (51) asg1 vreftop (54) 29 agndc (42) 42 36 (47) sc3_in_r 37 (46) sc3_in_l 35 (48) asg2 3 (15) s_da_in ana_in1+ (58) 25 ana_in2+ (60) 23 ana_in ? (59) 24 xtal_in (62) 21 xtal_out (63) 20 aud_cl_out (1) 18 testen (61) 22 daca_r (25) 60 3.3 f 10 f 7 (11) i 2 s_cl 12 (6) adr_sel 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 1 f 1 f 1 f 1 nf 1 nf 1 nf 1 nf 22 f 22 f 22 f 22 f 10 f 0.1 pf 50pf - + 100 nf 100 nf 100 nf 100 nf ahvss ahvss 27 (56) avss avss + 100 nf ++ 100 ? 100 ? 100 ? 100 ? + + + + + 10 f dvss dma_sync (64) 19 dvss 5v dvss 5v 8 (10) i 2 c-da 50pf 50pf ahvss 4 (14) i 2 s_da_in1 6 (12) i 2 s_ws d_ctr_out0 (5) 13 49 (35) vref1 58 (27) vref2 sc1_out_l (37) 47 sc1_out_r (36) 48 sc2_out_l (34) 50 sc2_out_r (33) 51 note: pin numbers refer to plcc packages, pin numbers for psdip packages in brackets. not connected pins are 2,10,15,16,17,38,39,40,41,53,54,55,62,63,64 (2,3,8,21,22,23,31,32,43,44,45) msp 3400c preliminary data sheet 65 micronas 10. dma application fig. 10 ? 1 shows an example for the d2mac application with the msp 3400 or msp 3400c. to obtain the optimal amplitude and phase conditions for the clock input of amu, dma 2386, and dma 2381, it is recommended to use a clock inverter circuit, as shown below right, a mini- mum gain of 1.0 at 18.432 mhz and an output phase as specified in fig. 10 ? 2. dma 2381 s_da_in s_data 66 sbs = 1 acs = 1 acf = 0 dcof= 1 (addr. 204, 214) aclk 18 aud_cl_out + 5 volt 5 k software: msp 3400c c6... msp 3410/00 tc15/f7 19 dma_sync mode_reg[0] = 1 1 s_id s_ident 64 s_clock 67 amu 2481 9 s_data_in s_data_out 6 s_bus slave_mode 65 17 16 13 audio_clock 68 s_cl 3 1 nf 15 s_ident 8 s_clock 18.432 mhz dma 2386 65 66 64 clock inverter (see below) aclk s_data s_ident 4.7 nf +2...3 v +5 v 100 nf 120 6k8 3k8 82 bc 848c to dma 2381/86 and amu 2481 10 nf clock inverter fig. 10 ? 1: dma application with msp 3410 tc15 or f7 open note: pin numbers refer to plcc packages for dma 2381 and msp 3400c and to psdip package for amu 2481 preliminary data sheet msp 3400c 66 micronas msp clock output clock inverter output timing window for the low to high edge at pin 17 of dma 2381 (xtal2) fig. 10 ? 2: timing requirements for the clock signal at the dma 2381 clock input typ. 20 ns at inverter output > 10 ns < 42 ns in the following table, the input/output clock-specification of the d2mac circuit is shown. table 10 ? 1: clock input and output specification for msps msp 3400c >c6 new version msp 3410/00 tc27 new version msp 3410/00 tc15 actual version xtal_in min (minimum amplitude) c input (after reset) > 0.7 vpp 22 pf > 0.7 vpp 22 pf > 0.7 vpp 31 pf aud_cl_out min with c load rout (hf) typ. > 1.2 vpp 40 pf 150 ? > 1.2 vpp 40 pf 120 ? > 1.0 vpp 43 pf 120 ? table 10 ? 2: clock input and output specification for ics connected to msp dma 2381 dma 2386 amu2481 xtal_in min clock-in min (minimal amplitude) c input > 0.7 vpp 24 pf 10 pf with: adr. 204,14=1 > 0.7 vpp 7pf > 0.7 vpp 7pf for the dma_sync input specification of the msp, please refer to page 54 ? v dmail , v dmaih . ? msp 3400c preliminary data sheet 67 micronas 11. msp application with external clock if for some reason, e.g. to spare the cost of an additional crystal, the msp receives the 18.432 mhz clock from an external source, for example from an other msp, the fol- lowing circuit can be used. for input/output specification see also table 10 ? 1. aud_cl_out 18 18.432 mhz msp 3400c or msp 3410b msp 3400c 62 xtal_in 63 62 10 nf lv fig. 11 ? 1: msp 3400c with external clock 63 xtal_out 12. adr application s_da_in s_id s_cl 18.432 mhz msp 3400c (in i 2 s slave mode) drp 3510a i 2 s_da_in i 2 s_ws i 2 s_cl tuner (sat) adr-interface i 2 s-interface i 2 s_da_out si1d si1i si1c so1d so1i so1c pi14 pi16 pi15 18.432 mhz preliminary data sheet msp 3400c 68 micronas 13. i 2 s bus in master/slave configuration with standby mode in a master/slave application, both msp, after power up and reset, will start as master by default. this means that before the slave msp is set to slave-mode, relatively large current-pulses (~20 ma) in the i2s_cl and i2s_ws lines can cause some crackling noise during startup time, if the the msp is demuted before the slave msp is set to slave mode. these high current pulses are also possible, if the active i2s_cl and i2s_ws outputs of the master msp are clipped by the correspondent inputs of the slave msp, which is switched to standby mode. to avoid this, it is recommended, that the i2s-bus lines i2s_cl and i2s_ws are current-limited to about 5 ma with series resistors of about 390 ? (330...470 ?). fig. 13 ? 1 depicts the recommended application circuit for two msp 3410/00 or msp 3400c, which are con- nected via i2s bus in a master/slave configuration, and where the slave msp can be switched in standby mode (+5 volt power is switched off). i2s_da_in 14 18.432 mhz msp 3410/00 msp 3400c (master) 63 62 fig. 13 ? 1: i 2 s master/slave application i2s_da_out 13 i2s_ws 12 i2s_cl 11 msp 3410/00 msp 3400c (slave) 18.432 mhz 63 62 7 18 +5 v 13 i2s_da_out 14 i2s_da_in 12 i2s_ws 11 i2s_cl dvsup standbyq standby control r c minimal corner frequency = 4 mhz with r = 390 ? (330 ? 470 ? ) msp 3400c preliminary data sheet 69 micronas 14. appendix a: technical code history tc01 first release, compatible with msp3410 and msp 3400. date: june 1994. tc04 emulator version for software development. version b5 new features: 1. equalizer 2. improved identification 3. improved adaptive deemphasis version c6 new features: 1. adjustable stereo basewidth enlargement (sbe) and switchable pseudo stereo effect (sbe) 2. new channel matrix modes (mono, sum/dif, etc) 3. new audio clock output driver 4. fast mute (volume) 5. clipping mode (volume) 6. sub db steps for volume, bass, treble, equalizer version c7 new features: 1. balance, bass, treble and loudness for headphone output 2. prescale for i2s1 and i2s2 inputs 3. balance in db units and linear mode 4. scart volume in db units and linear mode 5. increased range for bass/treble version c8 new features: 1. automatic volume control a.v.c. 2. subwoofer output alternatively with headphone out- put. 15. appendix b: documentation history 1. advance information: ? msp 3400c multistandard sound processor ? , apr. 14, 1994, 6251-377-1ai. first release of the advance information. 2. msp 3400c data sheet: ? msp 3400c multistandard sound processor ? , dec. 14, 1994, 6251-377-1pd. first release of the preliminary data sheet. 3. msp 3400c data sheet: ? msp 3400c multistandard sound processor ? , oct. 6, 1996, 6251-377-2pd. second release of the preliminary data sheet. major changes: see appendix a: version c6 4. msp 3400c data sheet: ? msp 3400c multistandard sound processor ? , dec. 8, 1997, 6251-377-3pd. third release of the preliminary data sheet. major changes: see appendix a: version c7 and c8 ? new pqfp80 package preliminary data sheet msp 3400c 70 micronas msp 3400c preliminary data sheet 71 micronas preliminary data sheet msp 3400c 72 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-377-3pd all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. by this publication, micronas gmbh does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. |
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